Lines 108-114
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|
108 |
* 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset. |
108 |
* 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset. |
109 |
* 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup. |
109 |
* 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup. |
110 |
* 0.55: 22 Mar 2006: Add flow control (pause frame). |
110 |
* 0.55: 22 Mar 2006: Add flow control (pause frame). |
111 |
* 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support. |
111 |
* 0.56: 22 Mar 2006: Additional ethtool and moduleparam support. |
|
|
112 |
* 0.57: 14 May 2006: Moved mac address writes to nv_probe and nv_remove. |
113 |
* 0.58: 20 May 2006: Optimized rx and tx data paths. |
114 |
* 0.59: 31 May 2006: Added support for sideband management unit. |
115 |
* 0.60: 31 May 2006: Added support for recoverable error. |
112 |
* |
116 |
* |
113 |
* Known bugs: |
117 |
* Known bugs: |
114 |
* We suspect that on some hardware no TX done interrupts are generated. |
118 |
* We suspect that on some hardware no TX done interrupts are generated. |
Lines 120-126
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|
120 |
* DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few |
124 |
* DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few |
121 |
* superfluous timer interrupts from the nic. |
125 |
* superfluous timer interrupts from the nic. |
122 |
*/ |
126 |
*/ |
123 |
#define FORCEDETH_VERSION "0.56" |
127 |
#define FORCEDETH_VERSION "0.60-Driver Package V1.21" |
124 |
#define DRV_NAME "forcedeth" |
128 |
#define DRV_NAME "forcedeth" |
125 |
|
129 |
|
126 |
#include <linux/module.h> |
130 |
#include <linux/module.h> |
Lines 138-156
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|
138 |
#include <linux/random.h> |
142 |
#include <linux/random.h> |
139 |
#include <linux/init.h> |
143 |
#include <linux/init.h> |
140 |
#include <linux/if_vlan.h> |
144 |
#include <linux/if_vlan.h> |
|
|
145 |
#include <linux/rtnetlink.h> |
146 |
#include <linux/version.h> |
147 |
|
148 |
#define RHES3 0 |
149 |
#define SLES9 1 |
150 |
#define RHES4 2 |
151 |
#define SUSE10 3 |
152 |
#define FEDORA5 4 |
153 |
|
154 |
|
155 |
#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13) |
156 |
#define NVVER FEDORA5 |
157 |
#elif LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9) |
158 |
#define NVVER SUSE10 |
159 |
#elif LINUX_VERSION_CODE > KERNEL_VERSION(2,6,6) |
160 |
#define NVVER RHES4 |
161 |
#elif LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) |
162 |
#define NVVER SLES9 |
163 |
#else |
164 |
#define NVVER RHES3 |
165 |
#endif |
166 |
|
167 |
#if NVVER > RHES3 |
141 |
#include <linux/dma-mapping.h> |
168 |
#include <linux/dma-mapping.h> |
|
|
169 |
#else |
170 |
#include <linux/forcedeth-compat.h> |
171 |
#endif |
142 |
|
172 |
|
143 |
#include <asm/irq.h> |
173 |
#include <asm/irq.h> |
144 |
#include <asm/io.h> |
174 |
#include <asm/io.h> |
145 |
#include <asm/uaccess.h> |
175 |
#include <asm/uaccess.h> |
146 |
#include <asm/system.h> |
176 |
#include <asm/system.h> |
147 |
|
177 |
|
148 |
#if 0 |
178 |
#ifdef NVLAN_DEBUG |
149 |
#define dprintk printk |
179 |
#define dprintk printk |
150 |
#else |
180 |
#else |
151 |
#define dprintk(x...) do { } while (0) |
181 |
#define dprintk(x...) do { } while (0) |
152 |
#endif |
182 |
#endif |
153 |
|
183 |
|
|
|
184 |
/* it should add in pci_ids.h */ |
185 |
#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_12 |
186 |
#define PCI_DEVICE_ID_NVIDIA_NVENET_12 0x0268 |
187 |
#endif |
188 |
#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_13 |
189 |
#define PCI_DEVICE_ID_NVIDIA_NVENET_13 0x0269 |
190 |
#endif |
191 |
#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_14 |
192 |
#define PCI_DEVICE_ID_NVIDIA_NVENET_14 0x0372 |
193 |
#endif |
194 |
#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_15 |
195 |
#define PCI_DEVICE_ID_NVIDIA_NVENET_15 0x0373 |
196 |
#endif |
197 |
#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_16 |
198 |
#define PCI_DEVICE_ID_NVIDIA_NVENET_16 0x03E5 |
199 |
#endif |
200 |
#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_17 |
201 |
#define PCI_DEVICE_ID_NVIDIA_NVENET_17 0x03E6 |
202 |
#endif |
203 |
#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_18 |
204 |
#define PCI_DEVICE_ID_NVIDIA_NVENET_18 0x03EE |
205 |
#endif |
206 |
#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_19 |
207 |
#define PCI_DEVICE_ID_NVIDIA_NVENET_19 0x03EF |
208 |
#endif |
209 |
#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_20 |
210 |
#define PCI_DEVICE_ID_NVIDIA_NVENET_20 0x0450 |
211 |
#endif |
212 |
#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_21 |
213 |
#define PCI_DEVICE_ID_NVIDIA_NVENET_21 0x0451 |
214 |
#endif |
215 |
#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_22 |
216 |
#define PCI_DEVICE_ID_NVIDIA_NVENET_22 0x0452 |
217 |
#endif |
218 |
#ifndef PCI_DEVICE_ID_NVIDIA_NVENET_23 |
219 |
#define PCI_DEVICE_ID_NVIDIA_NVENET_23 0x0453 |
220 |
#endif |
221 |
|
222 |
/* it should add in mii.h */ |
223 |
#ifndef ADVERTISE_1000HALF |
224 |
#define ADVERTISE_1000HALF 0x0100 |
225 |
#endif |
226 |
#ifndef ADVERTISE_1000FULL |
227 |
#define ADVERTISE_1000FULL 0x0200 |
228 |
#endif |
229 |
#ifndef ADVERTISE_PAUSE_CAP |
230 |
#define ADVERTISE_PAUSE_CAP 0x0400 |
231 |
#endif |
232 |
#ifndef ADVERTISE_PAUSE_ASYM |
233 |
#define ADVERTISE_PAUSE_ASYM 0x0800 |
234 |
#endif |
235 |
#ifndef MII_CTRL1000 |
236 |
#define MII_CTRL1000 0x09 |
237 |
#endif |
238 |
#ifndef MII_STAT1000 |
239 |
#define MII_STAT1000 0x0A |
240 |
#endif |
241 |
#ifndef LPA_1000FULL |
242 |
#define LPA_1000FULL 0x0800 |
243 |
#endif |
244 |
#ifndef LPA_1000HALF |
245 |
#define LPA_1000HALF 0x0400 |
246 |
#endif |
247 |
#ifndef LPA_PAUSE_CAP |
248 |
#define LPA_PAUSE_CAP 0x0400 |
249 |
#endif |
250 |
#ifndef LPA_PAUSE_ASYM |
251 |
#define LPA_PAUSE_ASYM 0x0800 |
252 |
#endif |
253 |
#ifndef BMCR_SPEED1000 |
254 |
#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ |
255 |
#endif |
256 |
|
257 |
#ifndef NETDEV_TX_OK |
258 |
#define NETDEV_TX_OK 0 /* driver took care of packet */ |
259 |
#endif |
260 |
|
261 |
#ifndef NETDEV_TX_BUSY |
262 |
#define NETDEV_TX_BUSY 1 /* driver tx path was busy*/ |
263 |
#endif |
264 |
|
265 |
#ifndef DMA_39BIT_MASK |
266 |
#define DMA_39BIT_MASK 0x0000007fffffffffULL |
267 |
#endif |
268 |
|
269 |
#ifndef __iomem |
270 |
#define __iomem |
271 |
#endif |
272 |
|
273 |
/* rx/tx mac addr + type + vlan + align + slack*/ |
274 |
#ifndef RX_NIC_BUFSIZE |
275 |
#define RX_NIC_BUFSIZE (ETH_DATA_LEN + 64) |
276 |
#endif |
277 |
/* even more slack */ |
278 |
#ifndef RX_ALLOC_BUFSIZE |
279 |
#define RX_ALLOC_BUFSIZE (ETH_DATA_LEN + 128) |
280 |
#endif |
281 |
|
282 |
#ifndef PCI_DEVICE |
283 |
#define PCI_DEVICE(vend,dev) \ |
284 |
.vendor = (vend), .device = (dev), \ |
285 |
.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID |
286 |
#endif |
287 |
|
288 |
#if NVVER < RHES4 |
289 |
struct msix_entry { |
290 |
u16 vector; /* kernel uses to write allocated vector */ |
291 |
u16 entry; /* driver uses to specify entry, OS writes */ |
292 |
}; |
293 |
#endif |
154 |
|
294 |
|
155 |
/* |
295 |
/* |
156 |
* Hardware access: |
296 |
* Hardware access: |
Lines 168-178
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|
168 |
#define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */ |
308 |
#define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */ |
169 |
#define DEV_HAS_STATISTICS 0x0400 /* device supports hw statistics */ |
309 |
#define DEV_HAS_STATISTICS 0x0400 /* device supports hw statistics */ |
170 |
#define DEV_HAS_TEST_EXTENDED 0x0800 /* device supports extended diagnostic test */ |
310 |
#define DEV_HAS_TEST_EXTENDED 0x0800 /* device supports extended diagnostic test */ |
|
|
311 |
#define DEV_HAS_MGMT_UNIT 0x1000 /* device supports management unit */ |
312 |
|
313 |
#define NVIDIA_ETHERNET_ID(deviceid,nv_driver_data) {\ |
314 |
.vendor = PCI_VENDOR_ID_NVIDIA, \ |
315 |
.device = deviceid, \ |
316 |
.subvendor = PCI_ANY_ID, \ |
317 |
.subdevice = PCI_ANY_ID, \ |
318 |
.driver_data = nv_driver_data, \ |
319 |
}, |
320 |
|
321 |
#define Mv_LED_Control 16 |
322 |
#define Mv_Page_Address 22 |
171 |
|
323 |
|
172 |
enum { |
324 |
enum { |
173 |
NvRegIrqStatus = 0x000, |
325 |
NvRegIrqStatus = 0x000, |
174 |
#define NVREG_IRQSTAT_MIIEVENT 0x040 |
326 |
#define NVREG_IRQSTAT_MIIEVENT 0x040 |
175 |
#define NVREG_IRQSTAT_MASK 0x1ff |
327 |
#define NVREG_IRQSTAT_MASK 0x81ff |
176 |
NvRegIrqMask = 0x004, |
328 |
NvRegIrqMask = 0x004, |
177 |
#define NVREG_IRQ_RX_ERROR 0x0001 |
329 |
#define NVREG_IRQ_RX_ERROR 0x0001 |
178 |
#define NVREG_IRQ_RX 0x0002 |
330 |
#define NVREG_IRQ_RX 0x0002 |
Lines 183-197
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|
183 |
#define NVREG_IRQ_LINK 0x0040 |
335 |
#define NVREG_IRQ_LINK 0x0040 |
184 |
#define NVREG_IRQ_RX_FORCED 0x0080 |
336 |
#define NVREG_IRQ_RX_FORCED 0x0080 |
185 |
#define NVREG_IRQ_TX_FORCED 0x0100 |
337 |
#define NVREG_IRQ_TX_FORCED 0x0100 |
|
|
338 |
#define NVREG_IRQ_RECOVER_ERROR 0x8000 |
186 |
#define NVREG_IRQMASK_THROUGHPUT 0x00df |
339 |
#define NVREG_IRQMASK_THROUGHPUT 0x00df |
187 |
#define NVREG_IRQMASK_CPU 0x0040 |
340 |
#define NVREG_IRQMASK_CPU 0x0040 |
188 |
#define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED) |
341 |
#define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED) |
189 |
#define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED) |
342 |
#define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED) |
190 |
#define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK) |
343 |
#define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR) |
191 |
|
344 |
|
192 |
#define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \ |
345 |
#define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \ |
193 |
NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \ |
346 |
NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \ |
194 |
NVREG_IRQ_TX_FORCED)) |
347 |
NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR)) |
195 |
|
348 |
|
196 |
NvRegUnknownSetupReg6 = 0x008, |
349 |
NvRegUnknownSetupReg6 = 0x008, |
197 |
#define NVREG_UNKSETUP6_VAL 3 |
350 |
#define NVREG_UNKSETUP6_VAL 3 |
Lines 216-221
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|
216 |
#define NVREG_MAC_RESET_ASSERT 0x0F3 |
369 |
#define NVREG_MAC_RESET_ASSERT 0x0F3 |
217 |
NvRegTransmitterControl = 0x084, |
370 |
NvRegTransmitterControl = 0x084, |
218 |
#define NVREG_XMITCTL_START 0x01 |
371 |
#define NVREG_XMITCTL_START 0x01 |
|
|
372 |
#define NVREG_XMITCTL_MGMT_ST 0x40000000 |
373 |
#define NVREG_XMITCTL_SYNC_MASK 0x000f0000 |
374 |
#define NVREG_XMITCTL_SYNC_NOT_READY 0x0 |
375 |
#define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000 |
376 |
#define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00 |
377 |
#define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0 |
378 |
#define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000 |
379 |
#define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000 |
380 |
#define NVREG_XMITCTL_HOST_LOADED 0x00004000 |
381 |
#define NVREG_XMITCTL_TX_PATH_EN 0x01000000 |
219 |
NvRegTransmitterStatus = 0x088, |
382 |
NvRegTransmitterStatus = 0x088, |
220 |
#define NVREG_XMITSTAT_BUSY 0x01 |
383 |
#define NVREG_XMITSTAT_BUSY 0x01 |
221 |
|
384 |
|
Lines 231-236
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|
231 |
#define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE |
394 |
#define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE |
232 |
NvRegReceiverControl = 0x094, |
395 |
NvRegReceiverControl = 0x094, |
233 |
#define NVREG_RCVCTL_START 0x01 |
396 |
#define NVREG_RCVCTL_START 0x01 |
|
|
397 |
#define NVREG_RCVCTL_RX_PATH_EN 0x01000000 |
234 |
NvRegReceiverStatus = 0x98, |
398 |
NvRegReceiverStatus = 0x98, |
235 |
#define NVREG_RCVSTAT_BUSY 0x01 |
399 |
#define NVREG_RCVSTAT_BUSY 0x01 |
236 |
|
400 |
|
Lines 241-247
Link Here
|
241 |
#define NVREG_RNDSEED_FORCE3 0x7400 |
405 |
#define NVREG_RNDSEED_FORCE3 0x7400 |
242 |
|
406 |
|
243 |
NvRegTxDeferral = 0xA0, |
407 |
NvRegTxDeferral = 0xA0, |
244 |
#define NVREG_TX_DEFERRAL_DEFAULT 0x15050f |
408 |
#define NVREG_TX_DEFERRAL_DEFAULT 0x15050f |
245 |
#define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f |
409 |
#define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f |
246 |
#define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f |
410 |
#define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f |
247 |
NvRegRxDeferral = 0xA4, |
411 |
NvRegRxDeferral = 0xA4, |
Lines 262-268
Link Here
|
262 |
NvRegRingSizes = 0x108, |
426 |
NvRegRingSizes = 0x108, |
263 |
#define NVREG_RINGSZ_TXSHIFT 0 |
427 |
#define NVREG_RINGSZ_TXSHIFT 0 |
264 |
#define NVREG_RINGSZ_RXSHIFT 16 |
428 |
#define NVREG_RINGSZ_RXSHIFT 16 |
265 |
NvRegUnknownTransmitterReg = 0x10c, |
429 |
NvRegTransmitPoll = 0x10c, |
|
|
430 |
#define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000 |
266 |
NvRegLinkSpeed = 0x110, |
431 |
NvRegLinkSpeed = 0x110, |
267 |
#define NVREG_LINKSPEED_FORCE 0x10000 |
432 |
#define NVREG_LINKSPEED_FORCE 0x10000 |
268 |
#define NVREG_LINKSPEED_10 1000 |
433 |
#define NVREG_LINKSPEED_10 1000 |
Lines 283-290
Link Here
|
283 |
#define NVREG_TXRXCTL_RESET 0x0010 |
448 |
#define NVREG_TXRXCTL_RESET 0x0010 |
284 |
#define NVREG_TXRXCTL_RXCHECK 0x0400 |
449 |
#define NVREG_TXRXCTL_RXCHECK 0x0400 |
285 |
#define NVREG_TXRXCTL_DESC_1 0 |
450 |
#define NVREG_TXRXCTL_DESC_1 0 |
286 |
#define NVREG_TXRXCTL_DESC_2 0x02100 |
451 |
#define NVREG_TXRXCTL_DESC_2 0x002100 |
287 |
#define NVREG_TXRXCTL_DESC_3 0x02200 |
452 |
#define NVREG_TXRXCTL_DESC_3 0xc02200 |
288 |
#define NVREG_TXRXCTL_VLANSTRIP 0x00040 |
453 |
#define NVREG_TXRXCTL_VLANSTRIP 0x00040 |
289 |
#define NVREG_TXRXCTL_VLANINS 0x00080 |
454 |
#define NVREG_TXRXCTL_VLANINS 0x00080 |
290 |
NvRegTxRingPhysAddrHigh = 0x148, |
455 |
NvRegTxRingPhysAddrHigh = 0x148, |
Lines 297-304
Link Here
|
297 |
#define NVREG_MIISTAT_LINKCHANGE 0x0008 |
462 |
#define NVREG_MIISTAT_LINKCHANGE 0x0008 |
298 |
#define NVREG_MIISTAT_MASK 0x000f |
463 |
#define NVREG_MIISTAT_MASK 0x000f |
299 |
#define NVREG_MIISTAT_MASK2 0x000f |
464 |
#define NVREG_MIISTAT_MASK2 0x000f |
300 |
NvRegUnknownSetupReg4 = 0x184, |
465 |
NvRegMIIMask = 0x184, |
301 |
#define NVREG_UNKSETUP4_VAL 8 |
466 |
#define NVREG_MII_LINKCHANGE 0x0008 |
302 |
|
467 |
|
303 |
NvRegAdapterControl = 0x188, |
468 |
NvRegAdapterControl = 0x188, |
304 |
#define NVREG_ADAPTCTL_START 0x02 |
469 |
#define NVREG_ADAPTCTL_START 0x02 |
Lines 328-333
Link Here
|
328 |
#define NVREG_WAKEUPFLAGS_ENABLE 0x1111 |
493 |
#define NVREG_WAKEUPFLAGS_ENABLE 0x1111 |
329 |
|
494 |
|
330 |
NvRegPatternCRC = 0x204, |
495 |
NvRegPatternCRC = 0x204, |
|
|
496 |
#define NV_UNKNOWN_VAL 0x01 |
331 |
NvRegPatternMask = 0x208, |
497 |
NvRegPatternMask = 0x208, |
332 |
NvRegPowerCap = 0x268, |
498 |
NvRegPowerCap = 0x268, |
333 |
#define NVREG_POWERCAP_D3SUPP (1<<30) |
499 |
#define NVREG_POWERCAP_D3SUPP (1<<30) |
Lines 368-373
Link Here
|
368 |
NvRegTxPause = 0x2e0, |
534 |
NvRegTxPause = 0x2e0, |
369 |
NvRegRxPause = 0x2e4, |
535 |
NvRegRxPause = 0x2e4, |
370 |
NvRegRxDropFrame = 0x2e8, |
536 |
NvRegRxDropFrame = 0x2e8, |
|
|
537 |
|
371 |
NvRegVlanControl = 0x300, |
538 |
NvRegVlanControl = 0x300, |
372 |
#define NVREG_VLANCONTROL_ENABLE 0x2000 |
539 |
#define NVREG_VLANCONTROL_ENABLE 0x2000 |
373 |
NvRegMSIXMap0 = 0x3e0, |
540 |
NvRegMSIXMap0 = 0x3e0, |
Lines 409-415
Link Here
|
409 |
#define NV_TX_CARRIERLOST (1<<27) |
576 |
#define NV_TX_CARRIERLOST (1<<27) |
410 |
#define NV_TX_LATECOLLISION (1<<28) |
577 |
#define NV_TX_LATECOLLISION (1<<28) |
411 |
#define NV_TX_UNDERFLOW (1<<29) |
578 |
#define NV_TX_UNDERFLOW (1<<29) |
412 |
#define NV_TX_ERROR (1<<30) |
579 |
#define NV_TX_ERROR (1<<30) /* logical OR of all errors */ |
413 |
#define NV_TX_VALID (1<<31) |
580 |
#define NV_TX_VALID (1<<31) |
414 |
|
581 |
|
415 |
#define NV_TX2_LASTPACKET (1<<29) |
582 |
#define NV_TX2_LASTPACKET (1<<29) |
Lines 420-426
Link Here
|
420 |
#define NV_TX2_LATECOLLISION (1<<27) |
587 |
#define NV_TX2_LATECOLLISION (1<<27) |
421 |
#define NV_TX2_UNDERFLOW (1<<28) |
588 |
#define NV_TX2_UNDERFLOW (1<<28) |
422 |
/* error and valid are the same for both */ |
589 |
/* error and valid are the same for both */ |
423 |
#define NV_TX2_ERROR (1<<30) |
590 |
#define NV_TX2_ERROR (1<<30) /* logical OR of all errors */ |
424 |
#define NV_TX2_VALID (1<<31) |
591 |
#define NV_TX2_VALID (1<<31) |
425 |
#define NV_TX2_TSO (1<<28) |
592 |
#define NV_TX2_TSO (1<<28) |
426 |
#define NV_TX2_TSO_SHIFT 14 |
593 |
#define NV_TX2_TSO_SHIFT 14 |
Lines 441-447
Link Here
|
441 |
#define NV_RX_CRCERR (1<<27) |
608 |
#define NV_RX_CRCERR (1<<27) |
442 |
#define NV_RX_OVERFLOW (1<<28) |
609 |
#define NV_RX_OVERFLOW (1<<28) |
443 |
#define NV_RX_FRAMINGERR (1<<29) |
610 |
#define NV_RX_FRAMINGERR (1<<29) |
444 |
#define NV_RX_ERROR (1<<30) |
611 |
#define NV_RX_ERROR (1<<30) /* logical OR of all errors */ |
445 |
#define NV_RX_AVAIL (1<<31) |
612 |
#define NV_RX_AVAIL (1<<31) |
446 |
|
613 |
|
447 |
#define NV_RX2_CHECKSUMMASK (0x1C000000) |
614 |
#define NV_RX2_CHECKSUMMASK (0x1C000000) |
Lines 458-464
Link Here
|
458 |
#define NV_RX2_OVERFLOW (1<<23) |
625 |
#define NV_RX2_OVERFLOW (1<<23) |
459 |
#define NV_RX2_FRAMINGERR (1<<24) |
626 |
#define NV_RX2_FRAMINGERR (1<<24) |
460 |
/* error and avail are the same for both */ |
627 |
/* error and avail are the same for both */ |
461 |
#define NV_RX2_ERROR (1<<30) |
628 |
#define NV_RX2_ERROR (1<<30) /* logical OR of all errors */ |
462 |
#define NV_RX2_AVAIL (1<<31) |
629 |
#define NV_RX2_AVAIL (1<<31) |
463 |
|
630 |
|
464 |
#define NV_RX3_VLAN_TAG_PRESENT (1<<16) |
631 |
#define NV_RX3_VLAN_TAG_PRESENT (1<<16) |
Lines 492-503
Link Here
|
492 |
#define NV_WATCHDOG_TIMEO (5*HZ) |
659 |
#define NV_WATCHDOG_TIMEO (5*HZ) |
493 |
|
660 |
|
494 |
#define RX_RING_DEFAULT 128 |
661 |
#define RX_RING_DEFAULT 128 |
495 |
#define TX_RING_DEFAULT 256 |
662 |
#define TX_RING_DEFAULT 64 |
496 |
#define RX_RING_MIN 128 |
663 |
#define RX_RING_MIN RX_RING_DEFAULT |
497 |
#define TX_RING_MIN 64 |
664 |
#define TX_RING_MIN TX_RING_DEFAULT |
498 |
#define RING_MAX_DESC_VER_1 1024 |
665 |
#define RING_MAX_DESC_VER_1 1024 |
499 |
#define RING_MAX_DESC_VER_2_3 16384 |
666 |
#define RING_MAX_DESC_VER_2_3 16384 |
500 |
/* |
667 |
/* |
501 |
* Difference between the get and put pointers for the tx ring. |
668 |
* Difference between the get and put pointers for the tx ring. |
502 |
* This is used to throttle the amount of data outstanding in the |
669 |
* This is used to throttle the amount of data outstanding in the |
503 |
* tx ring. |
670 |
* tx ring. |
Lines 518-524
Link Here
|
518 |
#define LINK_TIMEOUT (3*HZ) |
685 |
#define LINK_TIMEOUT (3*HZ) |
519 |
#define STATS_INTERVAL (10*HZ) |
686 |
#define STATS_INTERVAL (10*HZ) |
520 |
|
687 |
|
521 |
/* |
688 |
/* |
522 |
* desc_ver values: |
689 |
* desc_ver values: |
523 |
* The nic supports three different descriptor types: |
690 |
* The nic supports three different descriptor types: |
524 |
* - DESC_VER_1: Original |
691 |
* - DESC_VER_1: Original |
Lines 532-547
Link Here
|
532 |
/* PHY defines */ |
699 |
/* PHY defines */ |
533 |
#define PHY_OUI_MARVELL 0x5043 |
700 |
#define PHY_OUI_MARVELL 0x5043 |
534 |
#define PHY_OUI_CICADA 0x03f1 |
701 |
#define PHY_OUI_CICADA 0x03f1 |
|
|
702 |
#define PHY_OUI_VITESSE 0x01c1 |
535 |
#define PHYID1_OUI_MASK 0x03ff |
703 |
#define PHYID1_OUI_MASK 0x03ff |
536 |
#define PHYID1_OUI_SHFT 6 |
704 |
#define PHYID1_OUI_SHFT 6 |
537 |
#define PHYID2_OUI_MASK 0xfc00 |
705 |
#define PHYID2_OUI_MASK 0xfc00 |
538 |
#define PHYID2_OUI_SHFT 10 |
706 |
#define PHYID2_OUI_SHFT 10 |
539 |
#define PHY_INIT1 0x0f000 |
707 |
#define PHYID2_MODEL_MASK 0x03f0 |
540 |
#define PHY_INIT2 0x0e00 |
708 |
#define PHY_MODEL_MARVELL_E3016 0x220 |
541 |
#define PHY_INIT3 0x01000 |
709 |
#define PHY_MARVELL_E3016_INITMASK 0x0300 |
542 |
#define PHY_INIT4 0x0200 |
710 |
#define PHY_CICADA_INIT1 0x0f000 |
543 |
#define PHY_INIT5 0x0004 |
711 |
#define PHY_CICADA_INIT2 0x0e00 |
544 |
#define PHY_INIT6 0x02000 |
712 |
#define PHY_CICADA_INIT3 0x01000 |
|
|
713 |
#define PHY_CICADA_INIT4 0x0200 |
714 |
#define PHY_CICADA_INIT5 0x0004 |
715 |
#define PHY_CICADA_INIT6 0x02000 |
716 |
#define PHY_VITESSE_INIT_REG1 0x1f |
717 |
#define PHY_VITESSE_INIT_REG2 0x10 |
718 |
#define PHY_VITESSE_INIT_REG3 0x11 |
719 |
#define PHY_VITESSE_INIT_REG4 0x12 |
720 |
#define PHY_VITESSE_INIT_MSK1 0xc |
721 |
#define PHY_VITESSE_INIT_MSK2 0x0180 |
722 |
#define PHY_VITESSE_INIT1 0x52b5 |
723 |
#define PHY_VITESSE_INIT2 0xaf8a |
724 |
#define PHY_VITESSE_INIT3 0x8 |
725 |
#define PHY_VITESSE_INIT4 0x8f8a |
726 |
#define PHY_VITESSE_INIT5 0xaf86 |
727 |
#define PHY_VITESSE_INIT6 0x8f86 |
728 |
#define PHY_VITESSE_INIT7 0xaf82 |
729 |
#define PHY_VITESSE_INIT8 0x0100 |
730 |
#define PHY_VITESSE_INIT9 0x8f82 |
731 |
#define PHY_VITESSE_INIT10 0x0 |
732 |
|
545 |
#define PHY_GIGABIT 0x0100 |
733 |
#define PHY_GIGABIT 0x0100 |
546 |
|
734 |
|
547 |
#define PHY_TIMEOUT 0x1 |
735 |
#define PHY_TIMEOUT 0x1 |
Lines 573-644
Link Here
|
573 |
#define NV_MSI_X_VECTOR_OTHER 0x2 |
761 |
#define NV_MSI_X_VECTOR_OTHER 0x2 |
574 |
|
762 |
|
575 |
/* statistics */ |
763 |
/* statistics */ |
|
|
764 |
#define NV_STATS_COUNT_SW 10 |
765 |
|
766 |
#define NVLAN_DISABLE_ALL_FEATURES do { \ |
767 |
msi = NV_MSI_INT_DISABLED; \ |
768 |
msix = NV_MSIX_INT_DISABLED; \ |
769 |
scatter_gather = NV_SCATTER_GATHER_DISABLED; \ |
770 |
tso_offload = NV_TSO_DISABLED; \ |
771 |
tx_checksum_offload = NV_TX_CHECKSUM_DISABLED; \ |
772 |
rx_checksum_offload = NV_RX_CHECKSUM_DISABLED; \ |
773 |
tx_flow_control = NV_TX_FLOW_CONTROL_DISABLED; \ |
774 |
rx_flow_control = NV_RX_FLOW_CONTROL_DISABLED; \ |
775 |
wol = NV_WOL_DISABLED; \ |
776 |
tagging_8021pq = NV_8021PQ_DISABLED; \ |
777 |
} while (0) |
778 |
|
576 |
struct nv_ethtool_str { |
779 |
struct nv_ethtool_str { |
577 |
char name[ETH_GSTRING_LEN]; |
780 |
char name[ETH_GSTRING_LEN]; |
578 |
}; |
781 |
}; |
579 |
|
782 |
|
580 |
static const struct nv_ethtool_str nv_estats_str[] = { |
783 |
static const struct nv_ethtool_str nv_estats_str[] = { |
|
|
784 |
{ "tx_dropped" }, |
785 |
{ "tx_fifo_errors" }, |
786 |
{ "tx_carrier_errors" }, |
787 |
{ "tx_packets" }, |
581 |
{ "tx_bytes" }, |
788 |
{ "tx_bytes" }, |
|
|
789 |
{ "rx_crc_errors" }, |
790 |
{ "rx_over_errors" }, |
791 |
{ "rx_errors_total" }, |
792 |
{ "rx_packets" }, |
793 |
{ "rx_bytes" }, |
794 |
|
795 |
/* hardware counters */ |
582 |
{ "tx_zero_rexmt" }, |
796 |
{ "tx_zero_rexmt" }, |
583 |
{ "tx_one_rexmt" }, |
797 |
{ "tx_one_rexmt" }, |
584 |
{ "tx_many_rexmt" }, |
798 |
{ "tx_many_rexmt" }, |
585 |
{ "tx_late_collision" }, |
799 |
{ "tx_late_collision" }, |
586 |
{ "tx_fifo_errors" }, |
|
|
587 |
{ "tx_carrier_errors" }, |
588 |
{ "tx_excess_deferral" }, |
800 |
{ "tx_excess_deferral" }, |
589 |
{ "tx_retry_error" }, |
801 |
{ "tx_retry_error" }, |
590 |
{ "tx_deferral" }, |
|
|
591 |
{ "tx_packets" }, |
592 |
{ "tx_pause" }, |
593 |
{ "rx_frame_error" }, |
802 |
{ "rx_frame_error" }, |
594 |
{ "rx_extra_byte" }, |
803 |
{ "rx_extra_byte" }, |
595 |
{ "rx_late_collision" }, |
804 |
{ "rx_late_collision" }, |
596 |
{ "rx_runt" }, |
805 |
{ "rx_runt" }, |
597 |
{ "rx_frame_too_long" }, |
806 |
{ "rx_frame_too_long" }, |
598 |
{ "rx_over_errors" }, |
|
|
599 |
{ "rx_crc_errors" }, |
600 |
{ "rx_frame_align_error" }, |
807 |
{ "rx_frame_align_error" }, |
601 |
{ "rx_length_error" }, |
808 |
{ "rx_length_error" }, |
602 |
{ "rx_unicast" }, |
809 |
{ "rx_unicast" }, |
603 |
{ "rx_multicast" }, |
810 |
{ "rx_multicast" }, |
604 |
{ "rx_broadcast" }, |
811 |
{ "rx_broadcast" }, |
605 |
{ "rx_bytes" }, |
812 |
{ "tx_deferral" }, |
|
|
813 |
{ "tx_pause" }, |
606 |
{ "rx_pause" }, |
814 |
{ "rx_pause" }, |
607 |
{ "rx_drop_frame" }, |
815 |
{ "rx_drop_frame" } |
608 |
{ "rx_packets" }, |
|
|
609 |
{ "rx_errors_total" } |
610 |
}; |
816 |
}; |
611 |
|
817 |
|
612 |
struct nv_ethtool_stats { |
818 |
struct nv_ethtool_stats { |
|
|
819 |
u64 tx_dropped; |
820 |
u64 tx_fifo_errors; |
821 |
u64 tx_carrier_errors; |
822 |
u64 tx_packets; |
613 |
u64 tx_bytes; |
823 |
u64 tx_bytes; |
|
|
824 |
u64 rx_crc_errors; |
825 |
u64 rx_over_errors; |
826 |
u64 rx_errors_total; |
827 |
u64 rx_packets; |
828 |
u64 rx_bytes; |
829 |
|
830 |
/* hardware counters */ |
614 |
u64 tx_zero_rexmt; |
831 |
u64 tx_zero_rexmt; |
615 |
u64 tx_one_rexmt; |
832 |
u64 tx_one_rexmt; |
616 |
u64 tx_many_rexmt; |
833 |
u64 tx_many_rexmt; |
617 |
u64 tx_late_collision; |
834 |
u64 tx_late_collision; |
618 |
u64 tx_fifo_errors; |
|
|
619 |
u64 tx_carrier_errors; |
620 |
u64 tx_excess_deferral; |
835 |
u64 tx_excess_deferral; |
621 |
u64 tx_retry_error; |
836 |
u64 tx_retry_error; |
622 |
u64 tx_deferral; |
|
|
623 |
u64 tx_packets; |
624 |
u64 tx_pause; |
625 |
u64 rx_frame_error; |
837 |
u64 rx_frame_error; |
626 |
u64 rx_extra_byte; |
838 |
u64 rx_extra_byte; |
627 |
u64 rx_late_collision; |
839 |
u64 rx_late_collision; |
628 |
u64 rx_runt; |
840 |
u64 rx_runt; |
629 |
u64 rx_frame_too_long; |
841 |
u64 rx_frame_too_long; |
630 |
u64 rx_over_errors; |
|
|
631 |
u64 rx_crc_errors; |
632 |
u64 rx_frame_align_error; |
842 |
u64 rx_frame_align_error; |
633 |
u64 rx_length_error; |
843 |
u64 rx_length_error; |
634 |
u64 rx_unicast; |
844 |
u64 rx_unicast; |
635 |
u64 rx_multicast; |
845 |
u64 rx_multicast; |
636 |
u64 rx_broadcast; |
846 |
u64 rx_broadcast; |
637 |
u64 rx_bytes; |
847 |
u64 tx_deferral; |
|
|
848 |
u64 tx_pause; |
638 |
u64 rx_pause; |
849 |
u64 rx_pause; |
639 |
u64 rx_drop_frame; |
850 |
u64 rx_drop_frame; |
640 |
u64 rx_packets; |
|
|
641 |
u64 rx_errors_total; |
642 |
}; |
851 |
}; |
643 |
|
852 |
|
644 |
/* diagnostics */ |
853 |
/* diagnostics */ |
Lines 667-686
Link Here
|
667 |
{ 0,0 } |
876 |
{ 0,0 } |
668 |
}; |
877 |
}; |
669 |
|
878 |
|
|
|
879 |
struct nv_skb_map { |
880 |
struct sk_buff *skb; |
881 |
dma_addr_t dma; |
882 |
unsigned int dma_len; |
883 |
}; |
884 |
|
670 |
/* |
885 |
/* |
671 |
* SMP locking: |
886 |
* SMP locking: |
672 |
* All hardware access under dev->priv->lock, except the performance |
887 |
* All hardware access under dev->priv->lock, except the performance |
673 |
* critical parts: |
888 |
* critical parts: |
674 |
* - rx is (pseudo-) lockless: it relies on the single-threading provided |
889 |
* - rx is (pseudo-) lockless: it relies on the single-threading provided |
675 |
* by the arch code for interrupts. |
890 |
* by the arch code for interrupts. |
676 |
* - tx setup is lockless: it relies on netif_tx_lock. Actual submission |
891 |
* - tx setup is lockless: it relies on dev->xmit_lock. Actual submission |
677 |
* needs dev->priv->lock :-( |
892 |
* needs dev->priv->lock :-( |
678 |
* - set_multicast_list: preparation lockless, relies on netif_tx_lock. |
893 |
* - set_multicast_list: preparation lockless, relies on dev->xmit_lock. |
679 |
*/ |
894 |
*/ |
680 |
|
895 |
|
681 |
/* in dev: base, irq */ |
896 |
/* in dev: base, irq */ |
682 |
struct fe_priv { |
897 |
struct fe_priv { |
|
|
898 |
|
899 |
/* fields used in fast path are grouped together |
900 |
for better cache performance |
901 |
*/ |
683 |
spinlock_t lock; |
902 |
spinlock_t lock; |
|
|
903 |
void __iomem *base; |
904 |
struct pci_dev *pci_dev; |
905 |
u32 txrxctl_bits; |
906 |
int stop_tx; |
907 |
int need_linktimer; |
908 |
unsigned long link_timeout; |
909 |
u32 irqmask; |
910 |
u32 msi_flags; |
911 |
|
912 |
unsigned int rx_buf_sz; |
913 |
struct vlan_group *vlangrp; |
914 |
int tx_ring_size; |
915 |
int rx_csum; |
916 |
|
917 |
/* |
918 |
* rx specific fields in fast path |
919 |
*/ |
920 |
ring_type get_rx __attribute__((aligned(L1_CACHE_BYTES))); |
921 |
ring_type put_rx, first_rx, last_rx; |
922 |
struct nv_skb_map *get_rx_ctx, *put_rx_ctx; |
923 |
struct nv_skb_map *first_rx_ctx, *last_rx_ctx; |
924 |
|
925 |
/* |
926 |
* tx specific fields in fast path |
927 |
*/ |
928 |
ring_type get_tx __attribute__((aligned(L1_CACHE_BYTES))); |
929 |
ring_type put_tx, first_tx, last_tx; |
930 |
struct nv_skb_map *get_tx_ctx, *put_tx_ctx; |
931 |
struct nv_skb_map *first_tx_ctx, *last_tx_ctx; |
932 |
|
933 |
struct nv_skb_map *rx_skb; |
934 |
struct nv_skb_map *tx_skb; |
684 |
|
935 |
|
685 |
/* General data: |
936 |
/* General data: |
686 |
* Locking: spin_lock(&np->lock); */ |
937 |
* Locking: spin_lock(&np->lock); */ |
Lines 694-757
Link Here
|
694 |
int phyaddr; |
945 |
int phyaddr; |
695 |
int wolenabled; |
946 |
int wolenabled; |
696 |
unsigned int phy_oui; |
947 |
unsigned int phy_oui; |
|
|
948 |
unsigned int phy_model; |
697 |
u16 gigabit; |
949 |
u16 gigabit; |
698 |
int intr_test; |
950 |
int intr_test; |
|
|
951 |
int recover_error; |
699 |
|
952 |
|
700 |
/* General data: RO fields */ |
953 |
/* General data: RO fields */ |
701 |
dma_addr_t ring_addr; |
954 |
dma_addr_t ring_addr; |
702 |
struct pci_dev *pci_dev; |
|
|
703 |
u32 orig_mac[2]; |
955 |
u32 orig_mac[2]; |
704 |
u32 irqmask; |
|
|
705 |
u32 desc_ver; |
956 |
u32 desc_ver; |
706 |
u32 txrxctl_bits; |
|
|
707 |
u32 vlanctl_bits; |
957 |
u32 vlanctl_bits; |
708 |
u32 driver_data; |
958 |
u32 driver_data; |
709 |
u32 register_size; |
959 |
u32 register_size; |
710 |
|
960 |
u32 mac_in_use; |
711 |
void __iomem *base; |
|
|
712 |
|
961 |
|
713 |
/* rx specific fields. |
962 |
/* rx specific fields. |
714 |
* Locking: Within irq hander or disable_irq+spin_lock(&np->lock); |
963 |
* Locking: Within irq hander or disable_irq+spin_lock(&np->lock); |
715 |
*/ |
964 |
*/ |
716 |
ring_type rx_ring; |
965 |
ring_type rx_ring; |
717 |
unsigned int cur_rx, refill_rx; |
|
|
718 |
struct sk_buff **rx_skbuff; |
719 |
dma_addr_t *rx_dma; |
720 |
unsigned int rx_buf_sz; |
721 |
unsigned int pkt_limit; |
966 |
unsigned int pkt_limit; |
722 |
struct timer_list oom_kick; |
967 |
struct timer_list oom_kick; |
723 |
struct timer_list nic_poll; |
968 |
struct timer_list nic_poll; |
724 |
struct timer_list stats_poll; |
969 |
struct timer_list stats_poll; |
725 |
u32 nic_poll_irq; |
970 |
u32 nic_poll_irq; |
726 |
int rx_ring_size; |
971 |
int rx_ring_size; |
727 |
|
972 |
u32 rx_len_errors; |
728 |
/* media detection workaround. |
|
|
729 |
* Locking: Within irq hander or disable_irq+spin_lock(&np->lock); |
730 |
*/ |
731 |
int need_linktimer; |
732 |
unsigned long link_timeout; |
733 |
/* |
973 |
/* |
734 |
* tx specific fields. |
974 |
* tx specific fields. |
735 |
*/ |
975 |
*/ |
736 |
ring_type tx_ring; |
976 |
ring_type tx_ring; |
737 |
unsigned int next_tx, nic_tx; |
|
|
738 |
struct sk_buff **tx_skbuff; |
739 |
dma_addr_t *tx_dma; |
740 |
unsigned int *tx_dma_len; |
741 |
u32 tx_flags; |
977 |
u32 tx_flags; |
742 |
int tx_ring_size; |
|
|
743 |
int tx_limit_start; |
978 |
int tx_limit_start; |
744 |
int tx_limit_stop; |
979 |
int tx_limit_stop; |
745 |
|
980 |
|
746 |
/* vlan fields */ |
|
|
747 |
struct vlan_group *vlangrp; |
748 |
|
981 |
|
749 |
/* msi/msi-x fields */ |
982 |
/* msi/msi-x fields */ |
750 |
u32 msi_flags; |
|
|
751 |
struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS]; |
983 |
struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS]; |
752 |
|
984 |
|
753 |
/* flow control */ |
985 |
/* flow control */ |
754 |
u32 pause_flags; |
986 |
u32 pause_flags; |
|
|
987 |
u32 led_stats[3]; |
755 |
}; |
988 |
}; |
756 |
|
989 |
|
757 |
/* |
990 |
/* |
Lines 762-773
Link Here
|
762 |
|
995 |
|
763 |
/* |
996 |
/* |
764 |
* Optimization can be either throuput mode or cpu mode |
997 |
* Optimization can be either throuput mode or cpu mode |
765 |
* |
998 |
* |
766 |
* Throughput Mode: Every tx and rx packet will generate an interrupt. |
999 |
* Throughput Mode: Every tx and rx packet will generate an interrupt. |
767 |
* CPU Mode: Interrupts are controlled by a timer. |
1000 |
* CPU Mode: Interrupts are controlled by a timer. |
768 |
*/ |
1001 |
*/ |
769 |
enum { |
1002 |
enum { |
770 |
NV_OPTIMIZATION_MODE_THROUGHPUT, |
1003 |
NV_OPTIMIZATION_MODE_THROUGHPUT, |
771 |
NV_OPTIMIZATION_MODE_CPU |
1004 |
NV_OPTIMIZATION_MODE_CPU |
772 |
}; |
1005 |
}; |
773 |
static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT; |
1006 |
static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT; |
Lines 788-803
Link Here
|
788 |
NV_MSI_INT_DISABLED, |
1021 |
NV_MSI_INT_DISABLED, |
789 |
NV_MSI_INT_ENABLED |
1022 |
NV_MSI_INT_ENABLED |
790 |
}; |
1023 |
}; |
|
|
1024 |
|
1025 |
#ifdef CONFIG_PCI_MSI |
791 |
static int msi = NV_MSI_INT_ENABLED; |
1026 |
static int msi = NV_MSI_INT_ENABLED; |
|
|
1027 |
#else |
1028 |
static int msi = NV_MSI_INT_DISABLED; |
1029 |
#endif |
792 |
|
1030 |
|
793 |
/* |
1031 |
/* |
794 |
* MSIX interrupts |
1032 |
* MSIX interrupts |
795 |
*/ |
1033 |
*/ |
796 |
enum { |
1034 |
enum { |
797 |
NV_MSIX_INT_DISABLED, |
1035 |
NV_MSIX_INT_DISABLED, |
798 |
NV_MSIX_INT_ENABLED |
1036 |
NV_MSIX_INT_ENABLED |
799 |
}; |
1037 |
}; |
|
|
1038 |
|
1039 |
#ifdef CONFIG_PCI_MSI |
800 |
static int msix = NV_MSIX_INT_ENABLED; |
1040 |
static int msix = NV_MSIX_INT_ENABLED; |
|
|
1041 |
#else |
1042 |
static int msix = NV_MSIX_INT_DISABLED; |
1043 |
#endif |
1044 |
/* |
1045 |
* PHY Speed and Duplex |
1046 |
*/ |
1047 |
enum { |
1048 |
NV_SPEED_DUPLEX_AUTO, |
1049 |
NV_SPEED_DUPLEX_10_HALF_DUPLEX, |
1050 |
NV_SPEED_DUPLEX_10_FULL_DUPLEX, |
1051 |
NV_SPEED_DUPLEX_100_HALF_DUPLEX, |
1052 |
NV_SPEED_DUPLEX_100_FULL_DUPLEX, |
1053 |
NV_SPEED_DUPLEX_1000_FULL_DUPLEX |
1054 |
}; |
1055 |
static int speed_duplex = NV_SPEED_DUPLEX_AUTO; |
1056 |
|
1057 |
/* |
1058 |
* PHY autonegotiation |
1059 |
*/ |
1060 |
static int autoneg = AUTONEG_ENABLE; |
1061 |
|
1062 |
/* |
1063 |
* Scatter gather |
1064 |
*/ |
1065 |
enum { |
1066 |
NV_SCATTER_GATHER_DISABLED, |
1067 |
NV_SCATTER_GATHER_ENABLED |
1068 |
}; |
1069 |
static int scatter_gather = NV_SCATTER_GATHER_ENABLED; |
1070 |
|
1071 |
/* |
1072 |
* TCP Segmentation Offload (TSO) |
1073 |
*/ |
1074 |
enum { |
1075 |
NV_TSO_DISABLED, |
1076 |
NV_TSO_ENABLED |
1077 |
}; |
1078 |
static int tso_offload = NV_TSO_ENABLED; |
1079 |
|
1080 |
/* |
1081 |
* MTU settings |
1082 |
*/ |
1083 |
static int mtu = ETH_DATA_LEN; |
1084 |
|
1085 |
/* |
1086 |
* Tx checksum offload |
1087 |
*/ |
1088 |
enum { |
1089 |
NV_TX_CHECKSUM_DISABLED, |
1090 |
NV_TX_CHECKSUM_ENABLED |
1091 |
}; |
1092 |
static int tx_checksum_offload = NV_TX_CHECKSUM_ENABLED; |
1093 |
|
1094 |
/* |
1095 |
* Rx checksum offload |
1096 |
*/ |
1097 |
enum { |
1098 |
NV_RX_CHECKSUM_DISABLED, |
1099 |
NV_RX_CHECKSUM_ENABLED |
1100 |
}; |
1101 |
static int rx_checksum_offload = NV_RX_CHECKSUM_ENABLED; |
1102 |
|
1103 |
/* |
1104 |
* Tx ring size |
1105 |
*/ |
1106 |
static int tx_ring_size = TX_RING_DEFAULT; |
1107 |
|
1108 |
/* |
1109 |
* Rx ring size |
1110 |
*/ |
1111 |
static int rx_ring_size = RX_RING_DEFAULT; |
1112 |
|
1113 |
/* |
1114 |
* Tx flow control |
1115 |
*/ |
1116 |
enum { |
1117 |
NV_TX_FLOW_CONTROL_DISABLED, |
1118 |
NV_TX_FLOW_CONTROL_ENABLED |
1119 |
}; |
1120 |
static int tx_flow_control = NV_TX_FLOW_CONTROL_ENABLED; |
1121 |
|
1122 |
/* |
1123 |
* Rx flow control |
1124 |
*/ |
1125 |
enum { |
1126 |
NV_RX_FLOW_CONTROL_DISABLED, |
1127 |
NV_RX_FLOW_CONTROL_ENABLED |
1128 |
}; |
1129 |
static int rx_flow_control = NV_RX_FLOW_CONTROL_ENABLED; |
801 |
|
1130 |
|
802 |
/* |
1131 |
/* |
803 |
* DMA 64bit |
1132 |
* DMA 64bit |
Lines 808-821
Link Here
|
808 |
}; |
1137 |
}; |
809 |
static int dma_64bit = NV_DMA_64BIT_ENABLED; |
1138 |
static int dma_64bit = NV_DMA_64BIT_ENABLED; |
810 |
|
1139 |
|
|
|
1140 |
/* |
1141 |
* Wake On Lan |
1142 |
*/ |
1143 |
enum { |
1144 |
NV_WOL_DISABLED, |
1145 |
NV_WOL_ENABLED |
1146 |
}; |
1147 |
static int wol = NV_WOL_DISABLED; |
1148 |
|
1149 |
/* |
1150 |
* Tagging 802.1pq |
1151 |
*/ |
1152 |
enum { |
1153 |
NV_8021PQ_DISABLED, |
1154 |
NV_8021PQ_ENABLED |
1155 |
}; |
1156 |
static int tagging_8021pq = NV_8021PQ_ENABLED; |
1157 |
|
1158 |
#if NVVER < RHES4 |
1159 |
static inline unsigned long nv_msecs_to_jiffies(const unsigned int m) |
1160 |
{ |
1161 |
#if HZ <= 1000 && !(1000 % HZ) |
1162 |
return (m + (1000 / HZ) - 1) / (1000 / HZ); |
1163 |
#elif HZ > 1000 && !(HZ % 1000) |
1164 |
return m * (HZ / 1000); |
1165 |
#else |
1166 |
return (m * HZ + 999) / 1000; |
1167 |
#endif |
1168 |
} |
1169 |
#endif |
1170 |
|
1171 |
static void nv_msleep(unsigned int msecs) |
1172 |
{ |
1173 |
#if NVVER > SLES9 |
1174 |
msleep(msecs); |
1175 |
#else |
1176 |
unsigned long timeout = nv_msecs_to_jiffies(msecs); |
1177 |
|
1178 |
while (timeout) { |
1179 |
set_current_state(TASK_UNINTERRUPTIBLE); |
1180 |
timeout = schedule_timeout(timeout); |
1181 |
} |
1182 |
#endif |
1183 |
} |
1184 |
|
811 |
static inline struct fe_priv *get_nvpriv(struct net_device *dev) |
1185 |
static inline struct fe_priv *get_nvpriv(struct net_device *dev) |
812 |
{ |
1186 |
{ |
|
|
1187 |
#if NVVER > RHES3 |
813 |
return netdev_priv(dev); |
1188 |
return netdev_priv(dev); |
|
|
1189 |
#else |
1190 |
return (struct fe_priv *) dev->priv; |
1191 |
#endif |
1192 |
} |
1193 |
|
1194 |
static void __init quirk_nforce_network_class(struct pci_dev *pdev) |
1195 |
{ |
1196 |
/* Some implementations of the nVidia network controllers |
1197 |
* show up as bridges, when we need to see them as network |
1198 |
* devices. |
1199 |
*/ |
1200 |
|
1201 |
/* If this is already known as a network ctlr, do nothing. */ |
1202 |
if ((pdev->class >> 8) == PCI_CLASS_NETWORK_ETHERNET) |
1203 |
return; |
1204 |
|
1205 |
if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_OTHER) { |
1206 |
char c; |
1207 |
|
1208 |
/* Clearing bit 6 of the register at 0xf8 |
1209 |
* selects Ethernet device class |
1210 |
*/ |
1211 |
pci_read_config_byte(pdev, 0xf8, &c); |
1212 |
c &= 0xbf; |
1213 |
pci_write_config_byte(pdev, 0xf8, c); |
1214 |
|
1215 |
/* sysfs needs pdev->class to be set correctly */ |
1216 |
pdev->class &= 0x0000ff; |
1217 |
pdev->class |= (PCI_CLASS_NETWORK_ETHERNET << 8); |
1218 |
} |
814 |
} |
1219 |
} |
815 |
|
1220 |
|
816 |
static inline u8 __iomem *get_hwbase(struct net_device *dev) |
1221 |
static inline u8 __iomem *get_hwbase(struct net_device *dev) |
817 |
{ |
1222 |
{ |
818 |
return ((struct fe_priv *)netdev_priv(dev))->base; |
1223 |
return ((struct fe_priv *)get_nvpriv(dev))->base; |
819 |
} |
1224 |
} |
820 |
|
1225 |
|
821 |
static inline void pci_push(u8 __iomem *base) |
1226 |
static inline void pci_push(u8 __iomem *base) |
Lines 893-908
Link Here
|
893 |
pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size), |
1298 |
pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size), |
894 |
np->rx_ring.ex, np->ring_addr); |
1299 |
np->rx_ring.ex, np->ring_addr); |
895 |
} |
1300 |
} |
896 |
if (np->rx_skbuff) |
1301 |
if (np->rx_skb) |
897 |
kfree(np->rx_skbuff); |
1302 |
kfree(np->rx_skb); |
898 |
if (np->rx_dma) |
1303 |
if (np->tx_skb) |
899 |
kfree(np->rx_dma); |
1304 |
kfree(np->tx_skb); |
900 |
if (np->tx_skbuff) |
|
|
901 |
kfree(np->tx_skbuff); |
902 |
if (np->tx_dma) |
903 |
kfree(np->tx_dma); |
904 |
if (np->tx_dma_len) |
905 |
kfree(np->tx_dma_len); |
906 |
} |
1305 |
} |
907 |
|
1306 |
|
908 |
static int using_multi_irqs(struct net_device *dev) |
1307 |
static int using_multi_irqs(struct net_device *dev) |
Lines 910-916
Link Here
|
910 |
struct fe_priv *np = get_nvpriv(dev); |
1309 |
struct fe_priv *np = get_nvpriv(dev); |
911 |
|
1310 |
|
912 |
if (!(np->msi_flags & NV_MSI_X_ENABLED) || |
1311 |
if (!(np->msi_flags & NV_MSI_X_ENABLED) || |
913 |
((np->msi_flags & NV_MSI_X_ENABLED) && |
1312 |
((np->msi_flags & NV_MSI_X_ENABLED) && |
914 |
((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) |
1313 |
((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) |
915 |
return 0; |
1314 |
return 0; |
916 |
else |
1315 |
else |
Lines 921-926
Link Here
|
921 |
{ |
1320 |
{ |
922 |
struct fe_priv *np = get_nvpriv(dev); |
1321 |
struct fe_priv *np = get_nvpriv(dev); |
923 |
|
1322 |
|
|
|
1323 |
dprintk(KERN_DEBUG "%s: nv_enable_irq: begin\n",dev->name); |
1324 |
/* modify network device class id */ |
924 |
if (!using_multi_irqs(dev)) { |
1325 |
if (!using_multi_irqs(dev)) { |
925 |
if (np->msi_flags & NV_MSI_X_ENABLED) |
1326 |
if (np->msi_flags & NV_MSI_X_ENABLED) |
926 |
enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
1327 |
enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
Lines 937-942
Link Here
|
937 |
{ |
1338 |
{ |
938 |
struct fe_priv *np = get_nvpriv(dev); |
1339 |
struct fe_priv *np = get_nvpriv(dev); |
939 |
|
1340 |
|
|
|
1341 |
dprintk(KERN_DEBUG "%s: nv_disable_irq: begin\n",dev->name); |
940 |
if (!using_multi_irqs(dev)) { |
1342 |
if (!using_multi_irqs(dev)) { |
941 |
if (np->msi_flags & NV_MSI_X_ENABLED) |
1343 |
if (np->msi_flags & NV_MSI_X_ENABLED) |
942 |
disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
1344 |
disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
Lines 1020-1048
Link Here
|
1020 |
return retval; |
1422 |
return retval; |
1021 |
} |
1423 |
} |
1022 |
|
1424 |
|
1023 |
static int phy_reset(struct net_device *dev) |
1425 |
static void nv_save_LED_stats(struct net_device *dev) |
|
|
1426 |
{ |
1427 |
struct fe_priv *np = get_nvpriv(dev); |
1428 |
u32 reg=0; |
1429 |
u32 value=0; |
1430 |
int i=0; |
1431 |
|
1432 |
reg = Mv_Page_Address; |
1433 |
value = 3; |
1434 |
mii_rw(dev,np->phyaddr,reg,value); |
1435 |
udelay(5); |
1436 |
|
1437 |
reg = Mv_LED_Control; |
1438 |
for(i=0;i<3;i++){ |
1439 |
np->led_stats[i]=mii_rw(dev,np->phyaddr,reg+i,MII_READ); |
1440 |
dprintk(KERN_DEBUG "%s: save LED reg%d: value=0x%x\n",dev->name,reg+i,np->led_stats[i]); |
1441 |
} |
1442 |
|
1443 |
reg = Mv_Page_Address; |
1444 |
value = 0; |
1445 |
mii_rw(dev,np->phyaddr,reg,value); |
1446 |
udelay(5); |
1447 |
} |
1448 |
|
1449 |
static void nv_restore_LED_stats(struct net_device *dev) |
1450 |
{ |
1451 |
|
1452 |
struct fe_priv *np = get_nvpriv(dev); |
1453 |
u32 reg=0; |
1454 |
u32 value=0; |
1455 |
int i=0; |
1456 |
|
1457 |
reg = Mv_Page_Address; |
1458 |
value = 3; |
1459 |
mii_rw(dev,np->phyaddr,reg,value); |
1460 |
udelay(5); |
1461 |
|
1462 |
reg = Mv_LED_Control; |
1463 |
for(i=0;i<3;i++){ |
1464 |
mii_rw(dev,np->phyaddr,reg+i,np->led_stats[i]); |
1465 |
udelay(1); |
1466 |
dprintk(KERN_DEBUG "%s: restore LED reg%d: value=0x%x\n",dev->name,reg+i,np->led_stats[i]); |
1467 |
} |
1468 |
|
1469 |
reg = Mv_Page_Address; |
1470 |
value = 0; |
1471 |
mii_rw(dev,np->phyaddr,reg,value); |
1472 |
udelay(5); |
1473 |
} |
1474 |
|
1475 |
static int phy_reset(struct net_device *dev, u32 bmcr_setup) |
1024 |
{ |
1476 |
{ |
1025 |
struct fe_priv *np = netdev_priv(dev); |
1477 |
struct fe_priv *np = get_nvpriv(dev); |
1026 |
u32 miicontrol; |
1478 |
u32 miicontrol; |
1027 |
unsigned int tries = 0; |
1479 |
unsigned int tries = 0; |
1028 |
|
1480 |
|
1029 |
miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
1481 |
dprintk(KERN_DEBUG "%s: phy_reset: begin\n",dev->name); |
1030 |
miicontrol |= BMCR_RESET; |
1482 |
/**/ |
|
|
1483 |
nv_save_LED_stats(dev); |
1484 |
miicontrol = BMCR_RESET | bmcr_setup; |
1031 |
if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) { |
1485 |
if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) { |
1032 |
return -1; |
1486 |
return -1; |
1033 |
} |
1487 |
} |
1034 |
|
1488 |
|
1035 |
/* wait for 500ms */ |
1489 |
/* wait for 500ms */ |
1036 |
msleep(500); |
1490 |
nv_msleep(500); |
1037 |
|
1491 |
|
1038 |
/* must wait till reset is deasserted */ |
1492 |
/* must wait till reset is deasserted */ |
1039 |
while (miicontrol & BMCR_RESET) { |
1493 |
while (miicontrol & BMCR_RESET) { |
1040 |
msleep(10); |
1494 |
nv_msleep(10); |
1041 |
miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
1495 |
miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
1042 |
/* FIXME: 100 tries seem excessive */ |
1496 |
/* FIXME: 100 tries seem excessive */ |
1043 |
if (tries++ > 100) |
1497 |
if (tries++ > 100) |
1044 |
return -1; |
1498 |
return -1; |
1045 |
} |
1499 |
} |
|
|
1500 |
nv_restore_LED_stats(dev); |
1501 |
|
1046 |
return 0; |
1502 |
return 0; |
1047 |
} |
1503 |
} |
1048 |
|
1504 |
|
Lines 1052-1060
Link Here
|
1052 |
u8 __iomem *base = get_hwbase(dev); |
1508 |
u8 __iomem *base = get_hwbase(dev); |
1053 |
u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg; |
1509 |
u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg; |
1054 |
|
1510 |
|
|
|
1511 |
dprintk(KERN_DEBUG "%s: phy_init: begin\n",dev->name); |
1512 |
/* phy errata for E3016 phy */ |
1513 |
if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
1514 |
reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); |
1515 |
reg &= ~PHY_MARVELL_E3016_INITMASK; |
1516 |
if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { |
1517 |
printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev)); |
1518 |
return PHY_ERROR; |
1519 |
} |
1520 |
} |
1521 |
|
1055 |
/* set advertise register */ |
1522 |
/* set advertise register */ |
1056 |
reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
1523 |
reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
1057 |
reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP); |
1524 |
reg &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
|
|
1525 |
if (speed_duplex == NV_SPEED_DUPLEX_AUTO) |
1526 |
reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL); |
1527 |
if (speed_duplex == NV_SPEED_DUPLEX_10_HALF_DUPLEX) |
1528 |
reg |= ADVERTISE_10HALF; |
1529 |
if (speed_duplex == NV_SPEED_DUPLEX_10_FULL_DUPLEX) |
1530 |
reg |= ADVERTISE_10FULL; |
1531 |
if (speed_duplex == NV_SPEED_DUPLEX_100_HALF_DUPLEX) |
1532 |
reg |= ADVERTISE_100HALF; |
1533 |
if (speed_duplex == NV_SPEED_DUPLEX_100_FULL_DUPLEX) |
1534 |
reg |= ADVERTISE_100FULL; |
1535 |
if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */ |
1536 |
reg |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1537 |
if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) |
1538 |
reg |= ADVERTISE_PAUSE_ASYM; |
1539 |
np->fixed_mode = reg; |
1540 |
|
1058 |
if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { |
1541 |
if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { |
1059 |
printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev)); |
1542 |
printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev)); |
1060 |
return PHY_ERROR; |
1543 |
return PHY_ERROR; |
Lines 1069-1079
Link Here
|
1069 |
np->gigabit = PHY_GIGABIT; |
1552 |
np->gigabit = PHY_GIGABIT; |
1070 |
mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
1553 |
mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
1071 |
mii_control_1000 &= ~ADVERTISE_1000HALF; |
1554 |
mii_control_1000 &= ~ADVERTISE_1000HALF; |
1072 |
if (phyinterface & PHY_RGMII) |
1555 |
if (phyinterface & PHY_RGMII && |
|
|
1556 |
(speed_duplex == NV_SPEED_DUPLEX_AUTO || |
1557 |
(speed_duplex == NV_SPEED_DUPLEX_1000_FULL_DUPLEX && autoneg == AUTONEG_ENABLE))) |
1073 |
mii_control_1000 |= ADVERTISE_1000FULL; |
1558 |
mii_control_1000 |= ADVERTISE_1000FULL; |
1074 |
else |
1559 |
else { |
|
|
1560 |
if (speed_duplex == NV_SPEED_DUPLEX_1000_FULL_DUPLEX && autoneg == AUTONEG_DISABLE) |
1561 |
printk(KERN_INFO "%s: 1000mpbs full only allowed with autoneg\n", pci_name(np->pci_dev)); |
1075 |
mii_control_1000 &= ~ADVERTISE_1000FULL; |
1562 |
mii_control_1000 &= ~ADVERTISE_1000FULL; |
1076 |
|
1563 |
} |
1077 |
if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { |
1564 |
if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { |
1078 |
printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1565 |
printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1079 |
return PHY_ERROR; |
1566 |
return PHY_ERROR; |
Lines 1082-1089
Link Here
|
1082 |
else |
1569 |
else |
1083 |
np->gigabit = 0; |
1570 |
np->gigabit = 0; |
1084 |
|
1571 |
|
1085 |
/* reset the phy */ |
1572 |
mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
1086 |
if (phy_reset(dev)) { |
1573 |
if (autoneg == AUTONEG_DISABLE){ |
|
|
1574 |
np->pause_flags &= ~(NV_PAUSEFRAME_RX_ENABLE | NV_PAUSEFRAME_TX_ENABLE); |
1575 |
if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) |
1576 |
np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; |
1577 |
if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) |
1578 |
np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; |
1579 |
mii_control &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX); |
1580 |
if (reg & (ADVERTISE_10FULL|ADVERTISE_100FULL)) |
1581 |
mii_control |= BMCR_FULLDPLX; |
1582 |
if (reg & (ADVERTISE_100HALF|ADVERTISE_100FULL)) |
1583 |
mii_control |= BMCR_SPEED100; |
1584 |
} else { |
1585 |
mii_control |= BMCR_ANENABLE; |
1586 |
} |
1587 |
|
1588 |
/* reset the phy and setup BMCR |
1589 |
* (certain phys need reset at same time new values are set) */ |
1590 |
if (phy_reset(dev, mii_control)) { |
1087 |
printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev)); |
1591 |
printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev)); |
1088 |
return PHY_ERROR; |
1592 |
return PHY_ERROR; |
1089 |
} |
1593 |
} |
Lines 1091-1104
Link Here
|
1091 |
/* phy vendor specific configuration */ |
1595 |
/* phy vendor specific configuration */ |
1092 |
if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) { |
1596 |
if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) { |
1093 |
phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); |
1597 |
phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); |
1094 |
phy_reserved &= ~(PHY_INIT1 | PHY_INIT2); |
1598 |
phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2); |
1095 |
phy_reserved |= (PHY_INIT3 | PHY_INIT4); |
1599 |
phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4); |
1096 |
if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) { |
1600 |
if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) { |
1097 |
printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1601 |
printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1098 |
return PHY_ERROR; |
1602 |
return PHY_ERROR; |
1099 |
} |
1603 |
} |
1100 |
phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); |
1604 |
phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); |
1101 |
phy_reserved |= PHY_INIT5; |
1605 |
phy_reserved |= PHY_CICADA_INIT5; |
1102 |
if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) { |
1606 |
if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) { |
1103 |
printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1607 |
printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1104 |
return PHY_ERROR; |
1608 |
return PHY_ERROR; |
Lines 1106-1144
Link Here
|
1106 |
} |
1610 |
} |
1107 |
if (np->phy_oui == PHY_OUI_CICADA) { |
1611 |
if (np->phy_oui == PHY_OUI_CICADA) { |
1108 |
phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); |
1612 |
phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); |
1109 |
phy_reserved |= PHY_INIT6; |
1613 |
phy_reserved |= PHY_CICADA_INIT6; |
1110 |
if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) { |
1614 |
if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) { |
1111 |
printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1615 |
printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1112 |
return PHY_ERROR; |
1616 |
return PHY_ERROR; |
1113 |
} |
1617 |
} |
1114 |
} |
1618 |
} |
1115 |
/* some phys clear out pause advertisment on reset, set it back */ |
1619 |
if (np->phy_oui == PHY_OUI_VITESSE) { |
1116 |
mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg); |
1620 |
if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) { |
1117 |
|
1621 |
printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1118 |
/* restart auto negotiation */ |
1622 |
return PHY_ERROR; |
1119 |
mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
1623 |
} |
1120 |
mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); |
1624 |
if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) { |
1121 |
if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { |
1625 |
printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1122 |
return PHY_ERROR; |
1626 |
return PHY_ERROR; |
1123 |
} |
1627 |
} |
1124 |
|
1628 |
phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); |
1125 |
return 0; |
1629 |
if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { |
|
|
1630 |
printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1631 |
return PHY_ERROR; |
1632 |
} |
1633 |
phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); |
1634 |
phy_reserved &= ~PHY_VITESSE_INIT_MSK1; |
1635 |
phy_reserved |= PHY_VITESSE_INIT3; |
1636 |
if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { |
1637 |
printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1638 |
return PHY_ERROR; |
1639 |
} |
1640 |
if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) { |
1641 |
printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1642 |
return PHY_ERROR; |
1643 |
} |
1644 |
if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) { |
1645 |
printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1646 |
return PHY_ERROR; |
1647 |
} |
1648 |
phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); |
1649 |
phy_reserved &= ~PHY_VITESSE_INIT_MSK1; |
1650 |
phy_reserved |= PHY_VITESSE_INIT3; |
1651 |
if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { |
1652 |
printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1653 |
return PHY_ERROR; |
1654 |
} |
1655 |
phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); |
1656 |
if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { |
1657 |
printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1658 |
return PHY_ERROR; |
1659 |
} |
1660 |
if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) { |
1661 |
printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1662 |
return PHY_ERROR; |
1663 |
} |
1664 |
if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) { |
1665 |
printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1666 |
return PHY_ERROR; |
1667 |
} |
1668 |
phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); |
1669 |
if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { |
1670 |
printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1671 |
return PHY_ERROR; |
1672 |
} |
1673 |
phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); |
1674 |
phy_reserved &= ~PHY_VITESSE_INIT_MSK2; |
1675 |
phy_reserved |= PHY_VITESSE_INIT8; |
1676 |
if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { |
1677 |
printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1678 |
return PHY_ERROR; |
1679 |
} |
1680 |
if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) { |
1681 |
printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1682 |
return PHY_ERROR; |
1683 |
} |
1684 |
if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) { |
1685 |
printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); |
1686 |
return PHY_ERROR; |
1687 |
} |
1688 |
} |
1689 |
/* some phys clear out pause advertisment on reset, set it back */ |
1690 |
mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg); |
1691 |
|
1692 |
/* restart auto negotiation */ |
1693 |
if (autoneg == AUTONEG_ENABLE) { |
1694 |
mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
1695 |
mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); |
1696 |
if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { |
1697 |
return PHY_ERROR; |
1698 |
} |
1699 |
} |
1700 |
|
1701 |
return 0; |
1126 |
} |
1702 |
} |
1127 |
|
1703 |
|
1128 |
static void nv_start_rx(struct net_device *dev) |
1704 |
static void nv_start_rx(struct net_device *dev) |
1129 |
{ |
1705 |
{ |
1130 |
struct fe_priv *np = netdev_priv(dev); |
1706 |
struct fe_priv *np = get_nvpriv(dev); |
1131 |
u8 __iomem *base = get_hwbase(dev); |
1707 |
u8 __iomem *base = get_hwbase(dev); |
|
|
1708 |
u32 rx_ctrl = readl(base + NvRegReceiverControl); |
1132 |
|
1709 |
|
1133 |
dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name); |
1710 |
dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name); |
1134 |
/* Already running? Stop it. */ |
1711 |
/* Already running? Stop it. */ |
1135 |
if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) { |
1712 |
if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) { |
1136 |
writel(0, base + NvRegReceiverControl); |
1713 |
rx_ctrl &= ~NVREG_RCVCTL_START; |
|
|
1714 |
writel(rx_ctrl, base + NvRegReceiverControl); |
1137 |
pci_push(base); |
1715 |
pci_push(base); |
1138 |
} |
1716 |
} |
1139 |
writel(np->linkspeed, base + NvRegLinkSpeed); |
1717 |
writel(np->linkspeed, base + NvRegLinkSpeed); |
1140 |
pci_push(base); |
1718 |
pci_push(base); |
1141 |
writel(NVREG_RCVCTL_START, base + NvRegReceiverControl); |
1719 |
rx_ctrl |= NVREG_RCVCTL_START; |
|
|
1720 |
if (np->mac_in_use) |
1721 |
rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN; |
1722 |
writel(rx_ctrl, base + NvRegReceiverControl); |
1142 |
dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n", |
1723 |
dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n", |
1143 |
dev->name, np->duplex, np->linkspeed); |
1724 |
dev->name, np->duplex, np->linkspeed); |
1144 |
pci_push(base); |
1725 |
pci_push(base); |
Lines 1146-1189
Link Here
|
1146 |
|
1727 |
|
1147 |
static void nv_stop_rx(struct net_device *dev) |
1728 |
static void nv_stop_rx(struct net_device *dev) |
1148 |
{ |
1729 |
{ |
|
|
1730 |
struct fe_priv *np = get_nvpriv(dev); |
1149 |
u8 __iomem *base = get_hwbase(dev); |
1731 |
u8 __iomem *base = get_hwbase(dev); |
|
|
1732 |
u32 rx_ctrl = readl(base + NvRegReceiverControl); |
1150 |
|
1733 |
|
1151 |
dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name); |
1734 |
dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name); |
1152 |
writel(0, base + NvRegReceiverControl); |
1735 |
if (!np->mac_in_use) |
|
|
1736 |
rx_ctrl &= ~NVREG_RCVCTL_START; |
1737 |
else |
1738 |
rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN; |
1739 |
writel(rx_ctrl, base + NvRegReceiverControl); |
1153 |
reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, |
1740 |
reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, |
1154 |
NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX, |
1741 |
NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX, |
1155 |
KERN_INFO "nv_stop_rx: ReceiverStatus remained busy"); |
1742 |
KERN_INFO "nv_stop_rx: ReceiverStatus remained busy"); |
1156 |
|
1743 |
|
1157 |
udelay(NV_RXSTOP_DELAY2); |
1744 |
udelay(NV_RXSTOP_DELAY2); |
|
|
1745 |
if (!np->mac_in_use) |
1158 |
writel(0, base + NvRegLinkSpeed); |
1746 |
writel(0, base + NvRegLinkSpeed); |
1159 |
} |
1747 |
} |
1160 |
|
1748 |
|
1161 |
static void nv_start_tx(struct net_device *dev) |
1749 |
static void nv_start_tx(struct net_device *dev) |
1162 |
{ |
1750 |
{ |
|
|
1751 |
struct fe_priv *np = get_nvpriv(dev); |
1163 |
u8 __iomem *base = get_hwbase(dev); |
1752 |
u8 __iomem *base = get_hwbase(dev); |
|
|
1753 |
u32 tx_ctrl = readl(base + NvRegTransmitterControl); |
1164 |
|
1754 |
|
1165 |
dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name); |
1755 |
dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name); |
1166 |
writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl); |
1756 |
tx_ctrl |= NVREG_XMITCTL_START; |
|
|
1757 |
if (np->mac_in_use) |
1758 |
tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN; |
1759 |
writel(tx_ctrl, base + NvRegTransmitterControl); |
1167 |
pci_push(base); |
1760 |
pci_push(base); |
1168 |
} |
1761 |
} |
1169 |
|
1762 |
|
1170 |
static void nv_stop_tx(struct net_device *dev) |
1763 |
static void nv_stop_tx(struct net_device *dev) |
1171 |
{ |
1764 |
{ |
|
|
1765 |
struct fe_priv *np = get_nvpriv(dev); |
1172 |
u8 __iomem *base = get_hwbase(dev); |
1766 |
u8 __iomem *base = get_hwbase(dev); |
|
|
1767 |
u32 tx_ctrl = readl(base + NvRegTransmitterControl); |
1173 |
|
1768 |
|
1174 |
dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name); |
1769 |
dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name); |
1175 |
writel(0, base + NvRegTransmitterControl); |
1770 |
if (!np->mac_in_use) |
|
|
1771 |
tx_ctrl &= ~NVREG_XMITCTL_START; |
1772 |
else |
1773 |
tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN; |
1774 |
writel(tx_ctrl, base + NvRegTransmitterControl); |
1176 |
reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, |
1775 |
reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, |
1177 |
NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX, |
1776 |
NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX, |
1178 |
KERN_INFO "nv_stop_tx: TransmitterStatus remained busy"); |
1777 |
KERN_INFO "nv_stop_tx: TransmitterStatus remained busy"); |
1179 |
|
1778 |
|
1180 |
udelay(NV_TXSTOP_DELAY2); |
1779 |
udelay(NV_TXSTOP_DELAY2); |
1181 |
writel(0, base + NvRegUnknownTransmitterReg); |
1780 |
if (!np->mac_in_use) |
|
|
1781 |
writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); |
1182 |
} |
1782 |
} |
1183 |
|
1783 |
|
1184 |
static void nv_txrx_reset(struct net_device *dev) |
1784 |
static void nv_txrx_reset(struct net_device *dev) |
1185 |
{ |
1785 |
{ |
1186 |
struct fe_priv *np = netdev_priv(dev); |
1786 |
struct fe_priv *np = get_nvpriv(dev); |
1187 |
u8 __iomem *base = get_hwbase(dev); |
1787 |
u8 __iomem *base = get_hwbase(dev); |
1188 |
|
1788 |
|
1189 |
dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name); |
1789 |
dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name); |
Lines 1196-1202
Link Here
|
1196 |
|
1796 |
|
1197 |
static void nv_mac_reset(struct net_device *dev) |
1797 |
static void nv_mac_reset(struct net_device *dev) |
1198 |
{ |
1798 |
{ |
1199 |
struct fe_priv *np = netdev_priv(dev); |
1799 |
struct fe_priv *np = get_nvpriv(dev); |
1200 |
u8 __iomem *base = get_hwbase(dev); |
1800 |
u8 __iomem *base = get_hwbase(dev); |
1201 |
|
1801 |
|
1202 |
dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name); |
1802 |
dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name); |
Lines 1212-1286
Link Here
|
1212 |
pci_push(base); |
1812 |
pci_push(base); |
1213 |
} |
1813 |
} |
1214 |
|
1814 |
|
|
|
1815 |
#if NVVER < SLES9 |
1816 |
static int nv_ethtool_ioctl(struct net_device *dev, void *useraddr) |
1817 |
{ |
1818 |
struct fe_priv *np = get_nvpriv(dev); |
1819 |
u8 *base = get_hwbase(dev); |
1820 |
u32 ethcmd; |
1821 |
|
1822 |
if (copy_from_user(ðcmd, useraddr, sizeof (ethcmd))) |
1823 |
return -EFAULT; |
1824 |
|
1825 |
switch (ethcmd) { |
1826 |
case ETHTOOL_GDRVINFO: |
1827 |
{ |
1828 |
struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO }; |
1829 |
strcpy(info.driver, "forcedeth"); |
1830 |
strcpy(info.version, FORCEDETH_VERSION); |
1831 |
strcpy(info.bus_info, pci_name(np->pci_dev)); |
1832 |
if (copy_to_user(useraddr, &info, sizeof (info))) |
1833 |
return -EFAULT; |
1834 |
return 0; |
1835 |
} |
1836 |
case ETHTOOL_GLINK: |
1837 |
{ |
1838 |
struct ethtool_value edata = { ETHTOOL_GLINK }; |
1839 |
|
1840 |
edata.data = !!netif_carrier_ok(dev); |
1841 |
|
1842 |
if (copy_to_user(useraddr, &edata, sizeof(edata))) |
1843 |
return -EFAULT; |
1844 |
return 0; |
1845 |
} |
1846 |
case ETHTOOL_GWOL: |
1847 |
{ |
1848 |
struct ethtool_wolinfo wolinfo; |
1849 |
memset(&wolinfo, 0, sizeof(wolinfo)); |
1850 |
wolinfo.supported = WAKE_MAGIC; |
1851 |
|
1852 |
spin_lock_irq(&np->lock); |
1853 |
if (np->wolenabled) |
1854 |
wolinfo.wolopts = WAKE_MAGIC; |
1855 |
spin_unlock_irq(&np->lock); |
1856 |
|
1857 |
if (copy_to_user(useraddr, &wolinfo, sizeof(wolinfo))) |
1858 |
return -EFAULT; |
1859 |
return 0; |
1860 |
} |
1861 |
case ETHTOOL_SWOL: |
1862 |
{ |
1863 |
struct ethtool_wolinfo wolinfo; |
1864 |
if (copy_from_user(&wolinfo, useraddr, sizeof(wolinfo))) |
1865 |
return -EFAULT; |
1866 |
|
1867 |
spin_lock_irq(&np->lock); |
1868 |
if (wolinfo.wolopts == 0) { |
1869 |
writel(0, base + NvRegWakeUpFlags); |
1870 |
np->wolenabled = NV_WOL_DISABLED; |
1871 |
} |
1872 |
if (wolinfo.wolopts & WAKE_MAGIC) { |
1873 |
writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags); |
1874 |
np->wolenabled = NV_WOL_ENABLED; |
1875 |
} |
1876 |
spin_unlock_irq(&np->lock); |
1877 |
return 0; |
1878 |
} |
1879 |
|
1880 |
default: |
1881 |
break; |
1882 |
} |
1883 |
|
1884 |
return -EOPNOTSUPP; |
1885 |
} |
1886 |
|
1215 |
/* |
1887 |
/* |
1216 |
* nv_get_stats: dev->get_stats function |
1888 |
* nv_ioctl: dev->do_ioctl function |
1217 |
* Get latest stats value from the nic. |
1889 |
* Called with rtnl_lock held. |
1218 |
* Called with read_lock(&dev_base_lock) held for read - |
|
|
1219 |
* only synchronized against unregister_netdevice. |
1220 |
*/ |
1890 |
*/ |
1221 |
static struct net_device_stats *nv_get_stats(struct net_device *dev) |
1891 |
static int nv_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
1222 |
{ |
1892 |
{ |
1223 |
struct fe_priv *np = netdev_priv(dev); |
1893 |
switch(cmd) { |
|
|
1894 |
case SIOCETHTOOL: |
1895 |
return nv_ethtool_ioctl(dev, rq->ifr_data); |
1224 |
|
1896 |
|
1225 |
/* It seems that the nic always generates interrupts and doesn't |
1897 |
default: |
1226 |
* accumulate errors internally. Thus the current values in np->stats |
1898 |
return -EOPNOTSUPP; |
1227 |
* are already up to date. |
1899 |
} |
1228 |
*/ |
|
|
1229 |
return &np->stats; |
1230 |
} |
1900 |
} |
|
|
1901 |
#endif |
1231 |
|
1902 |
|
1232 |
/* |
1903 |
/* |
1233 |
* nv_alloc_rx: fill rx ring entries. |
1904 |
* nv_alloc_rx: fill rx ring entries. |
1234 |
* Return 1 if the allocations for the skbs failed and the |
1905 |
* Return 1 if the allocations for the skbs failed and the |
1235 |
* rx engine is without Available descriptors |
1906 |
* rx engine is without Available descriptors |
1236 |
*/ |
1907 |
*/ |
1237 |
static int nv_alloc_rx(struct net_device *dev) |
1908 |
static inline int nv_alloc_rx(struct net_device *dev) |
1238 |
{ |
1909 |
{ |
1239 |
struct fe_priv *np = netdev_priv(dev); |
1910 |
struct fe_priv *np = get_nvpriv(dev); |
1240 |
unsigned int refill_rx = np->refill_rx; |
1911 |
struct ring_desc* less_rx; |
1241 |
int nr; |
1912 |
struct sk_buff *skb; |
1242 |
|
|
|
1243 |
while (np->cur_rx != refill_rx) { |
1244 |
struct sk_buff *skb; |
1245 |
|
1246 |
nr = refill_rx % np->rx_ring_size; |
1247 |
if (np->rx_skbuff[nr] == NULL) { |
1248 |
|
1249 |
skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD); |
1250 |
if (!skb) |
1251 |
break; |
1252 |
|
1913 |
|
|
|
1914 |
less_rx = np->get_rx.orig; |
1915 |
if (less_rx-- == np->first_rx.orig) |
1916 |
less_rx = np->last_rx.orig; |
1917 |
|
1918 |
while (np->put_rx.orig != less_rx) { |
1919 |
skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD); |
1920 |
if (skb) { |
1253 |
skb->dev = dev; |
1921 |
skb->dev = dev; |
1254 |
np->rx_skbuff[nr] = skb; |
1922 |
np->put_rx_ctx->skb = skb; |
|
|
1923 |
np->put_rx_ctx->dma = pci_map_single(np->pci_dev, skb->data, |
1924 |
skb->end-skb->data, PCI_DMA_FROMDEVICE); |
1925 |
np->put_rx_ctx->dma_len = skb->end-skb->data; |
1926 |
np->put_rx.orig->PacketBuffer = cpu_to_le32(np->put_rx_ctx->dma); |
1927 |
wmb(); |
1928 |
np->put_rx.orig->FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL); |
1929 |
if (unlikely(np->put_rx.orig++ == np->last_rx.orig)) |
1930 |
np->put_rx.orig = np->first_rx.orig; |
1931 |
if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) |
1932 |
np->put_rx_ctx = np->first_rx_ctx; |
1255 |
} else { |
1933 |
} else { |
1256 |
skb = np->rx_skbuff[nr]; |
1934 |
return 1; |
1257 |
} |
1935 |
} |
1258 |
np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, |
1936 |
} |
1259 |
skb->end-skb->data, PCI_DMA_FROMDEVICE); |
1937 |
return 0; |
1260 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
1938 |
} |
1261 |
np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]); |
1939 |
|
|
|
1940 |
static inline int nv_alloc_rx_optimized(struct net_device *dev) |
1941 |
{ |
1942 |
struct fe_priv *np = get_nvpriv(dev); |
1943 |
struct ring_desc_ex* less_rx; |
1944 |
struct sk_buff *skb; |
1945 |
|
1946 |
less_rx = np->get_rx.ex; |
1947 |
if (less_rx-- == np->first_rx.ex) |
1948 |
less_rx = np->last_rx.ex; |
1949 |
|
1950 |
while (np->put_rx.ex != less_rx) { |
1951 |
skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD); |
1952 |
if (skb) { |
1953 |
skb->dev = dev; |
1954 |
np->put_rx_ctx->skb = skb; |
1955 |
np->put_rx_ctx->dma = pci_map_single(np->pci_dev, skb->data, |
1956 |
skb->end-skb->data, PCI_DMA_FROMDEVICE); |
1957 |
np->put_rx_ctx->dma_len = skb->end-skb->data; |
1958 |
np->put_rx.ex->PacketBufferHigh = cpu_to_le64(np->put_rx_ctx->dma) >> 32; |
1959 |
np->put_rx.ex->PacketBufferLow = cpu_to_le64(np->put_rx_ctx->dma) & 0x0FFFFFFFF; |
1262 |
wmb(); |
1960 |
wmb(); |
1263 |
np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL); |
1961 |
np->put_rx.ex->FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL); |
|
|
1962 |
if (unlikely(np->put_rx.ex++ == np->last_rx.ex)) |
1963 |
np->put_rx.ex = np->first_rx.ex; |
1964 |
if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) |
1965 |
np->put_rx_ctx = np->first_rx_ctx; |
1264 |
} else { |
1966 |
} else { |
1265 |
np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32; |
1967 |
return 1; |
1266 |
np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF; |
|
|
1267 |
wmb(); |
1268 |
np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL); |
1269 |
} |
1968 |
} |
1270 |
dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n", |
|
|
1271 |
dev->name, refill_rx); |
1272 |
refill_rx++; |
1273 |
} |
1969 |
} |
1274 |
np->refill_rx = refill_rx; |
|
|
1275 |
if (np->cur_rx - refill_rx == np->rx_ring_size) |
1276 |
return 1; |
1277 |
return 0; |
1970 |
return 0; |
|
|
1971 |
|
1278 |
} |
1972 |
} |
1279 |
|
1973 |
|
1280 |
static void nv_do_rx_refill(unsigned long data) |
1974 |
static void nv_do_rx_refill(unsigned long data) |
1281 |
{ |
1975 |
{ |
1282 |
struct net_device *dev = (struct net_device *) data; |
1976 |
struct net_device *dev = (struct net_device *) data; |
1283 |
struct fe_priv *np = netdev_priv(dev); |
1977 |
struct fe_priv *np = get_nvpriv(dev); |
|
|
1978 |
int retcode; |
1284 |
|
1979 |
|
1285 |
if (!using_multi_irqs(dev)) { |
1980 |
if (!using_multi_irqs(dev)) { |
1286 |
if (np->msi_flags & NV_MSI_X_ENABLED) |
1981 |
if (np->msi_flags & NV_MSI_X_ENABLED) |
Lines 1290-1296
Link Here
|
1290 |
} else { |
1985 |
} else { |
1291 |
disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
1986 |
disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
1292 |
} |
1987 |
} |
1293 |
if (nv_alloc_rx(dev)) { |
1988 |
|
|
|
1989 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
1990 |
retcode = nv_alloc_rx(dev); |
1991 |
else |
1992 |
retcode = nv_alloc_rx_optimized(dev); |
1993 |
if (retcode) { |
1294 |
spin_lock_irq(&np->lock); |
1994 |
spin_lock_irq(&np->lock); |
1295 |
if (!np->in_shutdown) |
1995 |
if (!np->in_shutdown) |
1296 |
mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
1996 |
mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
Lines 1306-1365
Link Here
|
1306 |
} |
2006 |
} |
1307 |
} |
2007 |
} |
1308 |
|
2008 |
|
1309 |
static void nv_init_rx(struct net_device *dev) |
2009 |
static void nv_init_rx(struct net_device *dev) |
1310 |
{ |
2010 |
{ |
1311 |
struct fe_priv *np = netdev_priv(dev); |
2011 |
struct fe_priv *np = get_nvpriv(dev); |
1312 |
int i; |
2012 |
int i; |
1313 |
|
2013 |
|
1314 |
np->cur_rx = np->rx_ring_size; |
2014 |
np->get_rx = np->put_rx = np->first_rx = np->rx_ring; |
1315 |
np->refill_rx = 0; |
|
|
1316 |
for (i = 0; i < np->rx_ring_size; i++) |
1317 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
2015 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
|
2016 |
np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1]; |
2017 |
else |
2018 |
np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1]; |
2019 |
np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb; |
2020 |
np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1]; |
2021 |
|
2022 |
for (i = 0; i < np->rx_ring_size; i++) { |
2023 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
1318 |
np->rx_ring.orig[i].FlagLen = 0; |
2024 |
np->rx_ring.orig[i].FlagLen = 0; |
1319 |
else |
2025 |
np->rx_ring.orig[i].PacketBuffer = 0; |
|
|
2026 |
} else { |
1320 |
np->rx_ring.ex[i].FlagLen = 0; |
2027 |
np->rx_ring.ex[i].FlagLen = 0; |
|
|
2028 |
np->rx_ring.ex[i].TxVlan = 0; |
2029 |
np->rx_ring.ex[i].PacketBufferHigh = 0; |
2030 |
np->rx_ring.ex[i].PacketBufferLow = 0; |
2031 |
} |
2032 |
np->rx_skb[i].skb = NULL; |
2033 |
np->rx_skb[i].dma = 0; |
2034 |
} |
1321 |
} |
2035 |
} |
1322 |
|
2036 |
|
1323 |
static void nv_init_tx(struct net_device *dev) |
2037 |
static void nv_init_tx(struct net_device *dev) |
1324 |
{ |
2038 |
{ |
1325 |
struct fe_priv *np = netdev_priv(dev); |
2039 |
struct fe_priv *np = get_nvpriv(dev); |
1326 |
int i; |
2040 |
int i; |
1327 |
|
2041 |
|
1328 |
np->next_tx = np->nic_tx = 0; |
2042 |
np->get_tx = np->put_tx = np->first_tx = np->tx_ring; |
|
|
2043 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
2044 |
np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1]; |
2045 |
else |
2046 |
np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1]; |
2047 |
np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb; |
2048 |
np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1]; |
2049 |
|
1329 |
for (i = 0; i < np->tx_ring_size; i++) { |
2050 |
for (i = 0; i < np->tx_ring_size; i++) { |
1330 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
2051 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
1331 |
np->tx_ring.orig[i].FlagLen = 0; |
2052 |
np->tx_ring.orig[i].FlagLen = 0; |
1332 |
else |
2053 |
np->tx_ring.orig[i].PacketBuffer = 0; |
|
|
2054 |
} else { |
1333 |
np->tx_ring.ex[i].FlagLen = 0; |
2055 |
np->tx_ring.ex[i].FlagLen = 0; |
1334 |
np->tx_skbuff[i] = NULL; |
2056 |
np->tx_ring.ex[i].TxVlan = 0; |
1335 |
np->tx_dma[i] = 0; |
2057 |
np->tx_ring.ex[i].PacketBufferHigh = 0; |
|
|
2058 |
np->tx_ring.ex[i].PacketBufferLow = 0; |
2059 |
} |
2060 |
np->tx_skb[i].skb = NULL; |
2061 |
np->tx_skb[i].dma = 0; |
1336 |
} |
2062 |
} |
1337 |
} |
2063 |
} |
1338 |
|
2064 |
|
1339 |
static int nv_init_ring(struct net_device *dev) |
2065 |
static int nv_init_ring(struct net_device *dev) |
1340 |
{ |
2066 |
{ |
|
|
2067 |
struct fe_priv *np = get_nvpriv(dev); |
1341 |
nv_init_tx(dev); |
2068 |
nv_init_tx(dev); |
1342 |
nv_init_rx(dev); |
2069 |
nv_init_rx(dev); |
1343 |
return nv_alloc_rx(dev); |
2070 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
|
2071 |
return nv_alloc_rx(dev); |
2072 |
else |
2073 |
return nv_alloc_rx_optimized(dev); |
1344 |
} |
2074 |
} |
1345 |
|
2075 |
|
1346 |
static int nv_release_txskb(struct net_device *dev, unsigned int skbnr) |
2076 |
static int nv_release_txskb(struct net_device *dev, unsigned int skbnr) |
1347 |
{ |
2077 |
{ |
1348 |
struct fe_priv *np = netdev_priv(dev); |
2078 |
struct fe_priv *np = get_nvpriv(dev); |
1349 |
|
2079 |
|
1350 |
dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n", |
2080 |
dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n", |
1351 |
dev->name, skbnr); |
2081 |
dev->name, skbnr); |
1352 |
|
2082 |
|
1353 |
if (np->tx_dma[skbnr]) { |
2083 |
if (np->tx_skb[skbnr].dma) { |
1354 |
pci_unmap_page(np->pci_dev, np->tx_dma[skbnr], |
2084 |
pci_unmap_page(np->pci_dev, np->tx_skb[skbnr].dma, |
1355 |
np->tx_dma_len[skbnr], |
2085 |
np->tx_skb[skbnr].dma_len, |
1356 |
PCI_DMA_TODEVICE); |
2086 |
PCI_DMA_TODEVICE); |
1357 |
np->tx_dma[skbnr] = 0; |
2087 |
np->tx_skb[skbnr].dma = 0; |
1358 |
} |
2088 |
} |
1359 |
|
2089 |
if (np->tx_skb[skbnr].skb) { |
1360 |
if (np->tx_skbuff[skbnr]) { |
2090 |
dev_kfree_skb_any(np->tx_skb[skbnr].skb); |
1361 |
dev_kfree_skb_any(np->tx_skbuff[skbnr]); |
2091 |
np->tx_skb[skbnr].skb = NULL; |
1362 |
np->tx_skbuff[skbnr] = NULL; |
|
|
1363 |
return 1; |
2092 |
return 1; |
1364 |
} else { |
2093 |
} else { |
1365 |
return 0; |
2094 |
return 0; |
Lines 1368-1381
Link Here
|
1368 |
|
2097 |
|
1369 |
static void nv_drain_tx(struct net_device *dev) |
2098 |
static void nv_drain_tx(struct net_device *dev) |
1370 |
{ |
2099 |
{ |
1371 |
struct fe_priv *np = netdev_priv(dev); |
2100 |
struct fe_priv *np = get_nvpriv(dev); |
1372 |
unsigned int i; |
2101 |
unsigned int i; |
1373 |
|
2102 |
|
1374 |
for (i = 0; i < np->tx_ring_size; i++) { |
2103 |
for (i = 0; i < np->tx_ring_size; i++) { |
1375 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
2104 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
1376 |
np->tx_ring.orig[i].FlagLen = 0; |
2105 |
np->tx_ring.orig[i].FlagLen = 0; |
1377 |
else |
2106 |
np->tx_ring.orig[i].PacketBuffer = 0; |
|
|
2107 |
} else { |
1378 |
np->tx_ring.ex[i].FlagLen = 0; |
2108 |
np->tx_ring.ex[i].FlagLen = 0; |
|
|
2109 |
np->tx_ring.ex[i].TxVlan = 0; |
2110 |
np->tx_ring.ex[i].PacketBufferHigh = 0; |
2111 |
np->tx_ring.ex[i].PacketBufferLow = 0; |
2112 |
} |
1379 |
if (nv_release_txskb(dev, i)) |
2113 |
if (nv_release_txskb(dev, i)) |
1380 |
np->stats.tx_dropped++; |
2114 |
np->stats.tx_dropped++; |
1381 |
} |
2115 |
} |
Lines 1383-1402
Link Here
|
1383 |
|
2117 |
|
1384 |
static void nv_drain_rx(struct net_device *dev) |
2118 |
static void nv_drain_rx(struct net_device *dev) |
1385 |
{ |
2119 |
{ |
1386 |
struct fe_priv *np = netdev_priv(dev); |
2120 |
struct fe_priv *np = get_nvpriv(dev); |
1387 |
int i; |
2121 |
int i; |
1388 |
for (i = 0; i < np->rx_ring_size; i++) { |
2122 |
for (i = 0; i < np->rx_ring_size; i++) { |
1389 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
2123 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
1390 |
np->rx_ring.orig[i].FlagLen = 0; |
2124 |
np->rx_ring.orig[i].FlagLen = 0; |
1391 |
else |
2125 |
np->rx_ring.orig[i].PacketBuffer = 0; |
|
|
2126 |
} else { |
1392 |
np->rx_ring.ex[i].FlagLen = 0; |
2127 |
np->rx_ring.ex[i].FlagLen = 0; |
|
|
2128 |
np->rx_ring.ex[i].TxVlan = 0; |
2129 |
np->rx_ring.ex[i].PacketBufferHigh = 0; |
2130 |
np->rx_ring.ex[i].PacketBufferLow = 0; |
2131 |
} |
1393 |
wmb(); |
2132 |
wmb(); |
1394 |
if (np->rx_skbuff[i]) { |
2133 |
if (np->rx_skb[i].skb) { |
1395 |
pci_unmap_single(np->pci_dev, np->rx_dma[i], |
2134 |
pci_unmap_single(np->pci_dev, np->rx_skb[i].dma, |
1396 |
np->rx_skbuff[i]->end-np->rx_skbuff[i]->data, |
2135 |
np->rx_skb[i].skb->end-np->rx_skb[i].skb->data, |
1397 |
PCI_DMA_FROMDEVICE); |
2136 |
PCI_DMA_FROMDEVICE); |
1398 |
dev_kfree_skb(np->rx_skbuff[i]); |
2137 |
dev_kfree_skb(np->rx_skb[i].skb); |
1399 |
np->rx_skbuff[i] = NULL; |
2138 |
np->rx_skb[i].skb = NULL; |
1400 |
} |
2139 |
} |
1401 |
} |
2140 |
} |
1402 |
} |
2141 |
} |
Lines 1409-1465
Link Here
|
1409 |
|
2148 |
|
1410 |
/* |
2149 |
/* |
1411 |
* nv_start_xmit: dev->hard_start_xmit function |
2150 |
* nv_start_xmit: dev->hard_start_xmit function |
1412 |
* Called with netif_tx_lock held. |
2151 |
* Called with dev->xmit_lock held. |
1413 |
*/ |
2152 |
*/ |
1414 |
static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev) |
2153 |
static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1415 |
{ |
2154 |
{ |
1416 |
struct fe_priv *np = netdev_priv(dev); |
2155 |
struct fe_priv *np = get_nvpriv(dev); |
1417 |
u32 tx_flags = 0; |
2156 |
u32 tx_flags = 0; |
1418 |
u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); |
2157 |
u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); |
1419 |
unsigned int fragments = skb_shinfo(skb)->nr_frags; |
2158 |
unsigned int fragments = skb_shinfo(skb)->nr_frags; |
1420 |
unsigned int nr = (np->next_tx - 1) % np->tx_ring_size; |
|
|
1421 |
unsigned int start_nr = np->next_tx % np->tx_ring_size; |
1422 |
unsigned int i; |
2159 |
unsigned int i; |
1423 |
u32 offset = 0; |
2160 |
u32 offset = 0; |
1424 |
u32 bcnt; |
2161 |
u32 bcnt; |
1425 |
u32 size = skb->len-skb->data_len; |
2162 |
u32 size = skb->len-skb->data_len; |
1426 |
u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
2163 |
u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
1427 |
u32 tx_flags_vlan = 0; |
2164 |
u32 empty_slots; |
|
|
2165 |
struct ring_desc* put_tx; |
2166 |
struct ring_desc* start_tx; |
2167 |
struct ring_desc* prev_tx; |
2168 |
struct nv_skb_map* prev_tx_ctx; |
1428 |
|
2169 |
|
|
|
2170 |
//dprintk(KERN_DEBUG "%s: nv_start_xmit \n", dev->name); |
1429 |
/* add fragments to entries count */ |
2171 |
/* add fragments to entries count */ |
1430 |
for (i = 0; i < fragments; i++) { |
2172 |
for (i = 0; i < fragments; i++) { |
1431 |
entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) + |
2173 |
entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) + |
1432 |
((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
2174 |
((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
1433 |
} |
2175 |
} |
1434 |
|
2176 |
|
1435 |
spin_lock_irq(&np->lock); |
2177 |
empty_slots = (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size)); |
|
|
2178 |
if (likely(empty_slots > entries)) { |
1436 |
|
2179 |
|
1437 |
if ((np->next_tx - np->nic_tx + entries - 1) > np->tx_limit_stop) { |
2180 |
start_tx = put_tx = np->put_tx.orig; |
1438 |
spin_unlock_irq(&np->lock); |
|
|
1439 |
netif_stop_queue(dev); |
1440 |
return NETDEV_TX_BUSY; |
1441 |
} |
1442 |
|
2181 |
|
1443 |
/* setup the header buffer */ |
2182 |
/* setup the header buffer */ |
1444 |
do { |
2183 |
do { |
|
|
2184 |
prev_tx = put_tx; |
2185 |
prev_tx_ctx = np->put_tx_ctx; |
1445 |
bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
2186 |
bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
1446 |
nr = (nr + 1) % np->tx_ring_size; |
2187 |
np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt, |
1447 |
|
|
|
1448 |
np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt, |
1449 |
PCI_DMA_TODEVICE); |
2188 |
PCI_DMA_TODEVICE); |
1450 |
np->tx_dma_len[nr] = bcnt; |
2189 |
np->put_tx_ctx->dma_len = bcnt; |
|
|
2190 |
put_tx->PacketBuffer = cpu_to_le32(np->put_tx_ctx->dma); |
2191 |
put_tx->FlagLen = cpu_to_le32((bcnt-1) | tx_flags); |
1451 |
|
2192 |
|
1452 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
|
|
1453 |
np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]); |
1454 |
np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags); |
1455 |
} else { |
1456 |
np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32; |
1457 |
np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF; |
1458 |
np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags); |
1459 |
} |
1460 |
tx_flags = np->tx_flags; |
2193 |
tx_flags = np->tx_flags; |
1461 |
offset += bcnt; |
2194 |
offset += bcnt; |
1462 |
size -= bcnt; |
2195 |
size -= bcnt; |
|
|
2196 |
if (unlikely(put_tx++ == np->last_tx.orig)) |
2197 |
put_tx = np->first_tx.orig; |
2198 |
if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
2199 |
np->put_tx_ctx = np->first_tx_ctx; |
1463 |
} while(size); |
2200 |
} while(size); |
1464 |
|
2201 |
|
1465 |
/* setup the fragments */ |
2202 |
/* setup the fragments */ |
Lines 1469-1502
Link Here
|
1469 |
offset = 0; |
2206 |
offset = 0; |
1470 |
|
2207 |
|
1471 |
do { |
2208 |
do { |
|
|
2209 |
prev_tx = put_tx; |
2210 |
prev_tx_ctx = np->put_tx_ctx; |
1472 |
bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
2211 |
bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
1473 |
nr = (nr + 1) % np->tx_ring_size; |
|
|
1474 |
|
2212 |
|
1475 |
np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt, |
2213 |
np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt, |
1476 |
PCI_DMA_TODEVICE); |
2214 |
PCI_DMA_TODEVICE); |
1477 |
np->tx_dma_len[nr] = bcnt; |
2215 |
np->put_tx_ctx->dma_len = bcnt; |
1478 |
|
2216 |
|
1479 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
2217 |
put_tx->PacketBuffer = cpu_to_le32(np->put_tx_ctx->dma); |
1480 |
np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]); |
2218 |
put_tx->FlagLen = cpu_to_le32((bcnt-1) | tx_flags); |
1481 |
np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags); |
|
|
1482 |
} else { |
1483 |
np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32; |
1484 |
np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF; |
1485 |
np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags); |
1486 |
} |
1487 |
offset += bcnt; |
2219 |
offset += bcnt; |
1488 |
size -= bcnt; |
2220 |
size -= bcnt; |
|
|
2221 |
if (unlikely(put_tx++ == np->last_tx.orig)) |
2222 |
put_tx = np->first_tx.orig; |
2223 |
if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
2224 |
np->put_tx_ctx = np->first_tx_ctx; |
1489 |
} while (size); |
2225 |
} while (size); |
1490 |
} |
2226 |
} |
1491 |
|
2227 |
|
1492 |
/* set last fragment flag */ |
2228 |
/* set last fragment flag */ |
1493 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
2229 |
prev_tx->FlagLen |= cpu_to_le32(tx_flags_extra); |
1494 |
np->tx_ring.orig[nr].FlagLen |= cpu_to_le32(tx_flags_extra); |
|
|
1495 |
} else { |
1496 |
np->tx_ring.ex[nr].FlagLen |= cpu_to_le32(tx_flags_extra); |
1497 |
} |
1498 |
|
2230 |
|
1499 |
np->tx_skbuff[nr] = skb; |
2231 |
/* save skb in this slot's context area */ |
|
|
2232 |
prev_tx_ctx->skb = skb; |
1500 |
|
2233 |
|
1501 |
#ifdef NETIF_F_TSO |
2234 |
#ifdef NETIF_F_TSO |
1502 |
if (skb_is_gso(skb)) |
2235 |
if (skb_is_gso(skb)) |
Lines 1505-1542
Link Here
|
1505 |
#endif |
2238 |
#endif |
1506 |
tx_flags_extra = (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0); |
2239 |
tx_flags_extra = (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0); |
1507 |
|
2240 |
|
1508 |
/* vlan tag */ |
2241 |
start_tx->FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra); |
1509 |
if (np->vlangrp && vlan_tx_tag_present(skb)) { |
2242 |
np->put_tx.orig = put_tx; |
1510 |
tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb); |
|
|
1511 |
} |
1512 |
|
2243 |
|
1513 |
/* set tx flags */ |
2244 |
dev->trans_start = jiffies; |
1514 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
2245 |
writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
1515 |
np->tx_ring.orig[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra); |
2246 |
return NETDEV_TX_OK; |
1516 |
} else { |
2247 |
} else { |
1517 |
np->tx_ring.ex[start_nr].TxVlan = cpu_to_le32(tx_flags_vlan); |
2248 |
netif_stop_queue(dev); |
1518 |
np->tx_ring.ex[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra); |
2249 |
np->stop_tx = 1; |
|
|
2250 |
return NETDEV_TX_BUSY; |
1519 |
} |
2251 |
} |
|
|
2252 |
} |
1520 |
|
2253 |
|
1521 |
dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n", |
2254 |
static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev) |
1522 |
dev->name, np->next_tx, entries, tx_flags_extra); |
2255 |
{ |
1523 |
{ |
2256 |
struct fe_priv *np = get_nvpriv(dev); |
1524 |
int j; |
2257 |
u32 tx_flags = 0; |
1525 |
for (j=0; j<64; j++) { |
2258 |
u32 tx_flags_extra; |
1526 |
if ((j%16) == 0) |
2259 |
unsigned int fragments = skb_shinfo(skb)->nr_frags; |
1527 |
dprintk("\n%03x:", j); |
2260 |
unsigned int i; |
1528 |
dprintk(" %02x", ((unsigned char*)skb->data)[j]); |
2261 |
u32 offset = 0; |
1529 |
} |
2262 |
u32 bcnt; |
1530 |
dprintk("\n"); |
2263 |
u32 size = skb->len-skb->data_len; |
|
|
2264 |
u32 empty_slots; |
2265 |
struct ring_desc_ex* put_tx; |
2266 |
struct ring_desc_ex* start_tx; |
2267 |
struct ring_desc_ex* prev_tx; |
2268 |
struct nv_skb_map* prev_tx_ctx; |
2269 |
|
2270 |
u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
2271 |
|
2272 |
//dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized \n", dev->name); |
2273 |
/* add fragments to entries count */ |
2274 |
for (i = 0; i < fragments; i++) { |
2275 |
entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) + |
2276 |
((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
1531 |
} |
2277 |
} |
1532 |
|
2278 |
|
1533 |
np->next_tx += entries; |
2279 |
empty_slots = (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size)); |
|
|
2280 |
if (likely(empty_slots > entries)) { |
2281 |
|
2282 |
start_tx = put_tx = np->put_tx.ex; |
2283 |
|
2284 |
/* setup the header buffer */ |
2285 |
do { |
2286 |
prev_tx = put_tx; |
2287 |
prev_tx_ctx = np->put_tx_ctx; |
2288 |
bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
2289 |
np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt, |
2290 |
PCI_DMA_TODEVICE); |
2291 |
np->put_tx_ctx->dma_len = bcnt; |
2292 |
put_tx->PacketBufferHigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32; |
2293 |
put_tx->PacketBufferLow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF; |
2294 |
put_tx->FlagLen = cpu_to_le32((bcnt-1) | tx_flags); |
2295 |
|
2296 |
tx_flags = NV_TX2_VALID; |
2297 |
offset += bcnt; |
2298 |
size -= bcnt; |
2299 |
if (unlikely(put_tx++ == np->last_tx.ex)) |
2300 |
put_tx = np->first_tx.ex; |
2301 |
if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
2302 |
np->put_tx_ctx = np->first_tx_ctx; |
2303 |
} while(size); |
2304 |
/* setup the fragments */ |
2305 |
for (i = 0; i < fragments; i++) { |
2306 |
skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
2307 |
u32 size = frag->size; |
2308 |
offset = 0; |
2309 |
|
2310 |
do { |
2311 |
prev_tx = put_tx; |
2312 |
prev_tx_ctx = np->put_tx_ctx; |
2313 |
bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
2314 |
|
2315 |
np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt, |
2316 |
PCI_DMA_TODEVICE); |
2317 |
np->put_tx_ctx->dma_len = bcnt; |
2318 |
|
2319 |
put_tx->PacketBufferHigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32; |
2320 |
put_tx->PacketBufferLow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF; |
2321 |
put_tx->FlagLen = cpu_to_le32((bcnt-1) | tx_flags); |
2322 |
offset += bcnt; |
2323 |
size -= bcnt; |
2324 |
if (unlikely(put_tx++ == np->last_tx.ex)) |
2325 |
put_tx = np->first_tx.ex; |
2326 |
if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
2327 |
np->put_tx_ctx = np->first_tx_ctx; |
2328 |
} while (size); |
2329 |
} |
2330 |
|
2331 |
/* set last fragment flag */ |
2332 |
prev_tx->FlagLen |= cpu_to_le32(NV_TX2_LASTPACKET); |
2333 |
|
2334 |
/* save skb in this slot's context area */ |
2335 |
prev_tx_ctx->skb = skb; |
2336 |
|
2337 |
#ifdef NETIF_F_TSO |
2338 |
if (skb_is_gso(skb)) |
2339 |
tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT); |
2340 |
else |
2341 |
#endif |
2342 |
tx_flags_extra = (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0); |
2343 |
|
2344 |
/* vlan tag */ |
2345 |
if (likely(!np->vlangrp)) { |
2346 |
start_tx->TxVlan = 0; |
2347 |
} else { |
2348 |
if (vlan_tx_tag_present(skb)) |
2349 |
start_tx->TxVlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb)); |
2350 |
else |
2351 |
start_tx->TxVlan = 0; |
2352 |
} |
2353 |
|
2354 |
/* set tx flags */ |
2355 |
start_tx->FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra); |
2356 |
np->put_tx.ex = put_tx; |
1534 |
|
2357 |
|
1535 |
dev->trans_start = jiffies; |
2358 |
dev->trans_start = jiffies; |
1536 |
spin_unlock_irq(&np->lock); |
|
|
1537 |
writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
2359 |
writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
1538 |
pci_push(get_hwbase(dev)); |
|
|
1539 |
return NETDEV_TX_OK; |
2360 |
return NETDEV_TX_OK; |
|
|
2361 |
|
2362 |
} else { |
2363 |
netif_stop_queue(dev); |
2364 |
np->stop_tx = 1; |
2365 |
return NETDEV_TX_BUSY; |
2366 |
} |
1540 |
} |
2367 |
} |
1541 |
|
2368 |
|
1542 |
/* |
2369 |
/* |
Lines 1544-1573
Link Here
|
1544 |
* |
2371 |
* |
1545 |
* Caller must own np->lock. |
2372 |
* Caller must own np->lock. |
1546 |
*/ |
2373 |
*/ |
1547 |
static void nv_tx_done(struct net_device *dev) |
2374 |
static inline void nv_tx_done(struct net_device *dev) |
1548 |
{ |
2375 |
{ |
1549 |
struct fe_priv *np = netdev_priv(dev); |
2376 |
struct fe_priv *np = get_nvpriv(dev); |
1550 |
u32 Flags; |
2377 |
u32 Flags; |
1551 |
unsigned int i; |
2378 |
struct ring_desc* orig_get_tx = np->get_tx.orig; |
1552 |
struct sk_buff *skb; |
2379 |
struct ring_desc* put_tx = np->put_tx.orig; |
1553 |
|
2380 |
|
1554 |
while (np->nic_tx != np->next_tx) { |
2381 |
//dprintk(KERN_DEBUG "%s: nv_tx_done \n", dev->name); |
1555 |
i = np->nic_tx % np->tx_ring_size; |
2382 |
while ((np->get_tx.orig != put_tx) && |
|
|
2383 |
!((Flags = le32_to_cpu(np->get_tx.orig->FlagLen)) & NV_TX_VALID)) { |
2384 |
dprintk(KERN_DEBUG "%s: nv_tx_done:NVLAN tx done\n", dev->name); |
1556 |
|
2385 |
|
1557 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
2386 |
pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma, |
1558 |
Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen); |
2387 |
np->get_tx_ctx->dma_len, |
1559 |
else |
2388 |
PCI_DMA_TODEVICE); |
1560 |
Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen); |
2389 |
np->get_tx_ctx->dma = 0; |
1561 |
|
2390 |
|
1562 |
dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n", |
|
|
1563 |
dev->name, np->nic_tx, Flags); |
1564 |
if (Flags & NV_TX_VALID) |
1565 |
break; |
1566 |
if (np->desc_ver == DESC_VER_1) { |
2391 |
if (np->desc_ver == DESC_VER_1) { |
1567 |
if (Flags & NV_TX_LASTPACKET) { |
2392 |
if (Flags & NV_TX_LASTPACKET) { |
1568 |
skb = np->tx_skbuff[i]; |
2393 |
if (Flags & NV_TX_ERROR) { |
1569 |
if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION| |
|
|
1570 |
NV_TX_UNDERFLOW|NV_TX_ERROR)) { |
1571 |
if (Flags & NV_TX_UNDERFLOW) |
2394 |
if (Flags & NV_TX_UNDERFLOW) |
1572 |
np->stats.tx_fifo_errors++; |
2395 |
np->stats.tx_fifo_errors++; |
1573 |
if (Flags & NV_TX_CARRIERLOST) |
2396 |
if (Flags & NV_TX_CARRIERLOST) |
Lines 1575-1588
Link Here
|
1575 |
np->stats.tx_errors++; |
2398 |
np->stats.tx_errors++; |
1576 |
} else { |
2399 |
} else { |
1577 |
np->stats.tx_packets++; |
2400 |
np->stats.tx_packets++; |
1578 |
np->stats.tx_bytes += skb->len; |
2401 |
np->stats.tx_bytes += np->get_tx_ctx->skb->len; |
1579 |
} |
2402 |
} |
|
|
2403 |
dev_kfree_skb_any(np->get_tx_ctx->skb); |
2404 |
np->get_tx_ctx->skb = NULL; |
2405 |
|
1580 |
} |
2406 |
} |
1581 |
} else { |
2407 |
} else { |
1582 |
if (Flags & NV_TX2_LASTPACKET) { |
2408 |
if (Flags & NV_TX2_LASTPACKET) { |
1583 |
skb = np->tx_skbuff[i]; |
2409 |
if (Flags & NV_TX2_ERROR) { |
1584 |
if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION| |
|
|
1585 |
NV_TX2_UNDERFLOW|NV_TX2_ERROR)) { |
1586 |
if (Flags & NV_TX2_UNDERFLOW) |
2410 |
if (Flags & NV_TX2_UNDERFLOW) |
1587 |
np->stats.tx_fifo_errors++; |
2411 |
np->stats.tx_fifo_errors++; |
1588 |
if (Flags & NV_TX2_CARRIERLOST) |
2412 |
if (Flags & NV_TX2_CARRIERLOST) |
Lines 1590-1616
Link Here
|
1590 |
np->stats.tx_errors++; |
2414 |
np->stats.tx_errors++; |
1591 |
} else { |
2415 |
} else { |
1592 |
np->stats.tx_packets++; |
2416 |
np->stats.tx_packets++; |
1593 |
np->stats.tx_bytes += skb->len; |
2417 |
np->stats.tx_bytes += np->get_tx_ctx->skb->len; |
1594 |
} |
2418 |
} |
|
|
2419 |
dev_kfree_skb_any(np->get_tx_ctx->skb); |
2420 |
np->get_tx_ctx->skb = NULL; |
1595 |
} |
2421 |
} |
1596 |
} |
2422 |
} |
1597 |
nv_release_txskb(dev, i); |
2423 |
|
1598 |
np->nic_tx++; |
2424 |
if (unlikely(np->get_tx.orig++ == np->last_tx.orig)) |
|
|
2425 |
np->get_tx.orig = np->first_tx.orig; |
2426 |
if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx)) |
2427 |
np->get_tx_ctx = np->first_tx_ctx; |
1599 |
} |
2428 |
} |
1600 |
if (np->next_tx - np->nic_tx < np->tx_limit_start) |
2429 |
if (unlikely((np->stop_tx == 1) && (np->get_tx.orig != orig_get_tx))) { |
|
|
2430 |
np->stop_tx = 0; |
1601 |
netif_wake_queue(dev); |
2431 |
netif_wake_queue(dev); |
|
|
2432 |
} |
2433 |
} |
2434 |
|
2435 |
static inline void nv_tx_done_optimized(struct net_device *dev, int max_work) |
2436 |
{ |
2437 |
struct fe_priv *np = get_nvpriv(dev); |
2438 |
u32 Flags; |
2439 |
struct ring_desc_ex* orig_get_tx = np->get_tx.ex; |
2440 |
struct ring_desc_ex* put_tx = np->put_tx.ex; |
2441 |
|
2442 |
//dprintk(KERN_DEBUG "%s: nv_tx_done_optimized \n", dev->name); |
2443 |
while ((np->get_tx.ex != put_tx) && |
2444 |
!((Flags = le32_to_cpu(np->get_tx.ex->FlagLen)) & NV_TX_VALID) && |
2445 |
(max_work-- > 0)) { |
2446 |
dprintk(KERN_DEBUG "%s: nv_tx_done_optimized:NVLAN tx done\n", dev->name); |
2447 |
|
2448 |
pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma, |
2449 |
np->get_tx_ctx->dma_len, |
2450 |
PCI_DMA_TODEVICE); |
2451 |
np->get_tx_ctx->dma = 0; |
2452 |
|
2453 |
if (Flags & NV_TX2_LASTPACKET) { |
2454 |
if (!(Flags & NV_TX2_ERROR)) { |
2455 |
np->stats.tx_packets++; |
2456 |
} |
2457 |
dev_kfree_skb_any(np->get_tx_ctx->skb); |
2458 |
np->get_tx_ctx->skb = NULL; |
2459 |
} |
2460 |
|
2461 |
if (unlikely(np->get_tx.ex++ == np->last_tx.ex)) |
2462 |
np->get_tx.ex = np->first_tx.ex; |
2463 |
if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx)) |
2464 |
np->get_tx_ctx = np->first_tx_ctx; |
2465 |
} |
2466 |
if (unlikely((np->stop_tx == 1) && (np->get_tx.ex != orig_get_tx))) { |
2467 |
np->stop_tx = 0; |
2468 |
netif_wake_queue(dev); |
2469 |
} |
1602 |
} |
2470 |
} |
1603 |
|
2471 |
|
1604 |
/* |
2472 |
/* |
1605 |
* nv_tx_timeout: dev->tx_timeout function |
2473 |
* nv_tx_timeout: dev->tx_timeout function |
1606 |
* Called with netif_tx_lock held. |
2474 |
* Called with dev->xmit_lock held. |
1607 |
*/ |
2475 |
*/ |
1608 |
static void nv_tx_timeout(struct net_device *dev) |
2476 |
static void nv_tx_timeout(struct net_device *dev) |
1609 |
{ |
2477 |
{ |
1610 |
struct fe_priv *np = netdev_priv(dev); |
2478 |
struct fe_priv *np = get_nvpriv(dev); |
1611 |
u8 __iomem *base = get_hwbase(dev); |
2479 |
u8 __iomem *base = get_hwbase(dev); |
1612 |
u32 status; |
2480 |
u32 status; |
1613 |
|
2481 |
|
|
|
2482 |
if (!netif_running(dev)) |
2483 |
return; |
2484 |
|
1614 |
if (np->msi_flags & NV_MSI_X_ENABLED) |
2485 |
if (np->msi_flags & NV_MSI_X_ENABLED) |
1615 |
status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; |
2486 |
status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; |
1616 |
else |
2487 |
else |
Lines 1621-1629
Link Here
|
1621 |
{ |
2492 |
{ |
1622 |
int i; |
2493 |
int i; |
1623 |
|
2494 |
|
1624 |
printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n", |
2495 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
1625 |
dev->name, (unsigned long)np->ring_addr, |
2496 |
printk(KERN_INFO "%s: Ring at %lx: get %lx put %lx\n", |
1626 |
np->next_tx, np->nic_tx); |
2497 |
dev->name, (unsigned long)np->tx_ring.orig, |
|
|
2498 |
(unsigned long)np->get_tx.orig, (unsigned long)np->put_tx.orig); |
2499 |
} else { |
2500 |
printk(KERN_INFO "%s: Ring at %lx: get %lx put %lx\n", |
2501 |
dev->name, (unsigned long)np->tx_ring.ex, |
2502 |
(unsigned long)np->get_tx.ex, (unsigned long)np->put_tx.ex); |
2503 |
} |
1627 |
printk(KERN_INFO "%s: Dumping tx registers\n", dev->name); |
2504 |
printk(KERN_INFO "%s: Dumping tx registers\n", dev->name); |
1628 |
for (i=0;i<=np->register_size;i+= 32) { |
2505 |
for (i=0;i<=np->register_size;i+= 32) { |
1629 |
printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n", |
2506 |
printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n", |
Lines 1637-1643
Link Here
|
1637 |
for (i=0;i<np->tx_ring_size;i+= 4) { |
2514 |
for (i=0;i<np->tx_ring_size;i+= 4) { |
1638 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
2515 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
1639 |
printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n", |
2516 |
printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n", |
1640 |
i, |
2517 |
i, |
1641 |
le32_to_cpu(np->tx_ring.orig[i].PacketBuffer), |
2518 |
le32_to_cpu(np->tx_ring.orig[i].PacketBuffer), |
1642 |
le32_to_cpu(np->tx_ring.orig[i].FlagLen), |
2519 |
le32_to_cpu(np->tx_ring.orig[i].FlagLen), |
1643 |
le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer), |
2520 |
le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer), |
Lines 1648-1654
Link Here
|
1648 |
le32_to_cpu(np->tx_ring.orig[i+3].FlagLen)); |
2525 |
le32_to_cpu(np->tx_ring.orig[i+3].FlagLen)); |
1649 |
} else { |
2526 |
} else { |
1650 |
printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n", |
2527 |
printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n", |
1651 |
i, |
2528 |
i, |
1652 |
le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh), |
2529 |
le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh), |
1653 |
le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow), |
2530 |
le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow), |
1654 |
le32_to_cpu(np->tx_ring.ex[i].FlagLen), |
2531 |
le32_to_cpu(np->tx_ring.ex[i].FlagLen), |
Lines 1665-1683
Link Here
|
1665 |
} |
2542 |
} |
1666 |
} |
2543 |
} |
1667 |
|
2544 |
|
|
|
2545 |
nv_disable_irq(dev); |
1668 |
spin_lock_irq(&np->lock); |
2546 |
spin_lock_irq(&np->lock); |
1669 |
|
2547 |
|
1670 |
/* 1) stop tx engine */ |
2548 |
/* 1) stop tx engine */ |
1671 |
nv_stop_tx(dev); |
2549 |
nv_stop_tx(dev); |
1672 |
|
2550 |
|
1673 |
/* 2) check that the packets were not sent already: */ |
2551 |
/* 2) check that the packets were not sent already: */ |
|
|
2552 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
1674 |
nv_tx_done(dev); |
2553 |
nv_tx_done(dev); |
|
|
2554 |
else |
2555 |
nv_tx_done_optimized(dev, np->tx_ring_size); |
1675 |
|
2556 |
|
1676 |
/* 3) if there are dead entries: clear everything */ |
2557 |
/* 3) if there are dead entries: clear everything */ |
1677 |
if (np->next_tx != np->nic_tx) { |
2558 |
if (np->get_tx_ctx != np->put_tx_ctx) { |
1678 |
printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name); |
2559 |
printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name); |
1679 |
nv_drain_tx(dev); |
2560 |
nv_drain_tx(dev); |
1680 |
np->next_tx = np->nic_tx = 0; |
2561 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
|
2562 |
np->get_tx.orig = np->put_tx.orig = np->first_tx.orig; |
2563 |
else |
2564 |
np->get_tx.ex = np->put_tx.ex = np->first_tx.ex; |
2565 |
np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx; |
1681 |
setup_hw_rings(dev, NV_SETUP_TX_RING); |
2566 |
setup_hw_rings(dev, NV_SETUP_TX_RING); |
1682 |
netif_wake_queue(dev); |
2567 |
netif_wake_queue(dev); |
1683 |
} |
2568 |
} |
Lines 1685-1690
Link Here
|
1685 |
/* 4) restart tx engine */ |
2570 |
/* 4) restart tx engine */ |
1686 |
nv_start_tx(dev); |
2571 |
nv_start_tx(dev); |
1687 |
spin_unlock_irq(&np->lock); |
2572 |
spin_unlock_irq(&np->lock); |
|
|
2573 |
nv_enable_irq(dev); |
1688 |
} |
2574 |
} |
1689 |
|
2575 |
|
1690 |
/* |
2576 |
/* |
Lines 1740-1782
Link Here
|
1740 |
} |
2626 |
} |
1741 |
} |
2627 |
} |
1742 |
|
2628 |
|
1743 |
static void nv_rx_process(struct net_device *dev) |
2629 |
static inline void nv_rx_process(struct net_device *dev) |
1744 |
{ |
2630 |
{ |
1745 |
struct fe_priv *np = netdev_priv(dev); |
2631 |
struct fe_priv *np = get_nvpriv(dev); |
1746 |
u32 Flags; |
2632 |
u32 Flags; |
1747 |
u32 vlanflags = 0; |
2633 |
struct sk_buff *skb; |
1748 |
|
2634 |
int len; |
1749 |
for (;;) { |
|
|
1750 |
struct sk_buff *skb; |
1751 |
int len; |
1752 |
int i; |
1753 |
if (np->cur_rx - np->refill_rx >= np->rx_ring_size) |
1754 |
break; /* we scanned the whole ring - do not continue */ |
1755 |
|
1756 |
i = np->cur_rx % np->rx_ring_size; |
1757 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
1758 |
Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen); |
1759 |
len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver); |
1760 |
} else { |
1761 |
Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen); |
1762 |
len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver); |
1763 |
vlanflags = le32_to_cpu(np->rx_ring.ex[i].PacketBufferLow); |
1764 |
} |
1765 |
|
2635 |
|
1766 |
dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n", |
2636 |
//dprintk(KERN_DEBUG "%s: nv_rx_process \n", dev->name); |
1767 |
dev->name, np->cur_rx, Flags); |
2637 |
while((np->get_rx.orig != np->put_rx.orig) && |
|
|
2638 |
!((Flags = le32_to_cpu(np->get_rx.orig->FlagLen)) & NV_RX_AVAIL)) { |
2639 |
|
2640 |
pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma, |
2641 |
np->get_rx_ctx->dma_len, |
2642 |
PCI_DMA_FROMDEVICE); |
1768 |
|
2643 |
|
1769 |
if (Flags & NV_RX_AVAIL) |
2644 |
skb = np->get_rx_ctx->skb; |
1770 |
break; /* still owned by hardware, */ |
2645 |
np->get_rx_ctx->skb = NULL; |
1771 |
|
|
|
1772 |
/* |
1773 |
* the packet is for us - immediately tear down the pci mapping. |
1774 |
* TODO: check if a prefetch of the first cacheline improves |
1775 |
* the performance. |
1776 |
*/ |
1777 |
pci_unmap_single(np->pci_dev, np->rx_dma[i], |
1778 |
np->rx_skbuff[i]->end-np->rx_skbuff[i]->data, |
1779 |
PCI_DMA_FROMDEVICE); |
1780 |
|
2646 |
|
1781 |
{ |
2647 |
{ |
1782 |
int j; |
2648 |
int j; |
Lines 1784-1901
Link Here
|
1784 |
for (j=0; j<64; j++) { |
2650 |
for (j=0; j<64; j++) { |
1785 |
if ((j%16) == 0) |
2651 |
if ((j%16) == 0) |
1786 |
dprintk("\n%03x:", j); |
2652 |
dprintk("\n%03x:", j); |
1787 |
dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]); |
2653 |
dprintk(" %02x", ((unsigned char*)skb->data)[j]); |
1788 |
} |
2654 |
} |
1789 |
dprintk("\n"); |
2655 |
dprintk("\n"); |
1790 |
} |
2656 |
} |
1791 |
/* look at what we actually got: */ |
2657 |
|
1792 |
if (np->desc_ver == DESC_VER_1) { |
2658 |
if (np->desc_ver == DESC_VER_1) { |
1793 |
if (!(Flags & NV_RX_DESCRIPTORVALID)) |
|
|
1794 |
goto next_pkt; |
1795 |
|
2659 |
|
1796 |
if (Flags & NV_RX_ERROR) { |
2660 |
if (likely(Flags & NV_RX_DESCRIPTORVALID)) { |
1797 |
if (Flags & NV_RX_MISSEDFRAME) { |
2661 |
len = Flags & LEN_MASK_V1; |
1798 |
np->stats.rx_missed_errors++; |
2662 |
if (unlikely(Flags & NV_RX_ERROR)) { |
1799 |
np->stats.rx_errors++; |
2663 |
if (Flags & NV_RX_ERROR4) { |
1800 |
goto next_pkt; |
2664 |
len = nv_getlen(dev, skb->data, len); |
1801 |
} |
2665 |
if (len < 0) { |
1802 |
if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) { |
2666 |
np->stats.rx_errors++; |
1803 |
np->stats.rx_errors++; |
2667 |
dev_kfree_skb(skb); |
1804 |
goto next_pkt; |
2668 |
goto next_pkt; |
1805 |
} |
2669 |
} |
1806 |
if (Flags & NV_RX_CRCERR) { |
2670 |
} |
1807 |
np->stats.rx_crc_errors++; |
2671 |
/* framing errors are soft errors */ |
1808 |
np->stats.rx_errors++; |
2672 |
else if (Flags & NV_RX_FRAMINGERR) { |
1809 |
goto next_pkt; |
2673 |
if (Flags & NV_RX_SUBSTRACT1) { |
1810 |
} |
2674 |
len--; |
1811 |
if (Flags & NV_RX_OVERFLOW) { |
2675 |
} |
1812 |
np->stats.rx_over_errors++; |
2676 |
} |
1813 |
np->stats.rx_errors++; |
2677 |
/* the rest are hard errors */ |
1814 |
goto next_pkt; |
2678 |
else { |
|
|
2679 |
if (Flags & NV_RX_MISSEDFRAME) |
2680 |
np->stats.rx_missed_errors++; |
2681 |
if (Flags & NV_RX_CRCERR) |
2682 |
np->stats.rx_crc_errors++; |
2683 |
if (Flags & NV_RX_OVERFLOW) |
2684 |
np->stats.rx_over_errors++; |
2685 |
np->stats.rx_errors++; |
2686 |
dev_kfree_skb(skb); |
2687 |
goto next_pkt; |
2688 |
} |
1815 |
} |
2689 |
} |
1816 |
if (Flags & NV_RX_ERROR4) { |
2690 |
} else { |
1817 |
len = nv_getlen(dev, np->rx_skbuff[i]->data, len); |
2691 |
dev_kfree_skb(skb); |
1818 |
if (len < 0) { |
2692 |
goto next_pkt; |
|
|
2693 |
} |
2694 |
} else { |
2695 |
if (likely(Flags & NV_RX2_DESCRIPTORVALID)) { |
2696 |
len = Flags & LEN_MASK_V2; |
2697 |
if (unlikely(Flags & NV_RX2_ERROR)) { |
2698 |
if (Flags & NV_RX2_ERROR4) { |
2699 |
len = nv_getlen(dev, skb->data, len); |
2700 |
if (len < 0) { |
2701 |
np->stats.rx_errors++; |
2702 |
dev_kfree_skb(skb); |
2703 |
goto next_pkt; |
2704 |
} |
2705 |
} |
2706 |
/* framing errors are soft errors */ |
2707 |
else if (Flags & NV_RX2_FRAMINGERR) { |
2708 |
if (Flags & NV_RX2_SUBSTRACT1) { |
2709 |
len--; |
2710 |
} |
2711 |
} |
2712 |
/* the rest are hard errors */ |
2713 |
else { |
2714 |
if (Flags & NV_RX2_CRCERR) |
2715 |
np->stats.rx_crc_errors++; |
2716 |
if (Flags & NV_RX2_OVERFLOW) |
2717 |
np->stats.rx_over_errors++; |
1819 |
np->stats.rx_errors++; |
2718 |
np->stats.rx_errors++; |
|
|
2719 |
dev_kfree_skb(skb); |
1820 |
goto next_pkt; |
2720 |
goto next_pkt; |
1821 |
} |
2721 |
} |
1822 |
} |
2722 |
} |
1823 |
/* framing errors are soft errors. */ |
2723 |
if ((Flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK2)/*ip and tcp */ { |
1824 |
if (Flags & NV_RX_FRAMINGERR) { |
2724 |
skb->ip_summed = CHECKSUM_UNNECESSARY; |
1825 |
if (Flags & NV_RX_SUBSTRACT1) { |
2725 |
} else { |
1826 |
len--; |
2726 |
if ((Flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK1 || |
|
|
2727 |
(Flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK3) { |
2728 |
skb->ip_summed = CHECKSUM_UNNECESSARY; |
1827 |
} |
2729 |
} |
1828 |
} |
2730 |
} |
1829 |
} |
2731 |
} else { |
1830 |
} else { |
2732 |
dev_kfree_skb(skb); |
1831 |
if (!(Flags & NV_RX2_DESCRIPTORVALID)) |
|
|
1832 |
goto next_pkt; |
2733 |
goto next_pkt; |
|
|
2734 |
} |
2735 |
} |
2736 |
|
2737 |
/* got a valid packet - forward it to the network core */ |
2738 |
dprintk(KERN_DEBUG "%s: nv_rx_process:NVLAN rx done\n", dev->name); |
2739 |
skb_put(skb, len); |
2740 |
skb->protocol = eth_type_trans(skb, dev); |
2741 |
netif_rx(skb); |
2742 |
dev->last_rx = jiffies; |
2743 |
np->stats.rx_packets++; |
2744 |
np->stats.rx_bytes += len; |
2745 |
next_pkt: |
2746 |
if (unlikely(np->get_rx.orig++ == np->last_rx.orig)) |
2747 |
np->get_rx.orig = np->first_rx.orig; |
2748 |
if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx)) |
2749 |
np->get_rx_ctx = np->first_rx_ctx; |
2750 |
} |
2751 |
} |
1833 |
|
2752 |
|
1834 |
if (Flags & NV_RX2_ERROR) { |
2753 |
static inline int nv_rx_process_optimized(struct net_device *dev, int max_work) |
1835 |
if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) { |
2754 |
{ |
1836 |
np->stats.rx_errors++; |
2755 |
struct fe_priv *np = get_nvpriv(dev); |
1837 |
goto next_pkt; |
2756 |
u32 Flags; |
1838 |
} |
2757 |
u32 vlanflags = 0; |
1839 |
if (Flags & NV_RX2_CRCERR) { |
2758 |
u32 rx_processed_cnt = 0; |
1840 |
np->stats.rx_crc_errors++; |
2759 |
struct sk_buff *skb; |
1841 |
np->stats.rx_errors++; |
2760 |
int len; |
1842 |
goto next_pkt; |
2761 |
|
1843 |
} |
2762 |
// dprintk(KERN_DEBUG "%s: nv_rx_process_optimized \n", dev->name); |
1844 |
if (Flags & NV_RX2_OVERFLOW) { |
2763 |
while((np->get_rx.ex != np->put_rx.ex) && |
1845 |
np->stats.rx_over_errors++; |
2764 |
!((Flags = le32_to_cpu(np->get_rx.ex->FlagLen)) & NV_RX2_AVAIL) && |
1846 |
np->stats.rx_errors++; |
2765 |
(rx_processed_cnt++ < max_work)) { |
1847 |
goto next_pkt; |
2766 |
|
1848 |
} |
2767 |
pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma, |
|
|
2768 |
np->get_rx_ctx->dma_len, |
2769 |
PCI_DMA_FROMDEVICE); |
2770 |
|
2771 |
skb = np->get_rx_ctx->skb; |
2772 |
np->get_rx_ctx->skb = NULL; |
2773 |
|
2774 |
/* look at what we actually got: */ |
2775 |
if (likely(Flags & NV_RX2_DESCRIPTORVALID)) { |
2776 |
len = Flags & LEN_MASK_V2; |
2777 |
if (unlikely(Flags & NV_RX2_ERROR)) { |
1849 |
if (Flags & NV_RX2_ERROR4) { |
2778 |
if (Flags & NV_RX2_ERROR4) { |
1850 |
len = nv_getlen(dev, np->rx_skbuff[i]->data, len); |
2779 |
len = nv_getlen(dev, skb->data, len); |
1851 |
if (len < 0) { |
2780 |
if (len < 0) { |
1852 |
np->stats.rx_errors++; |
2781 |
np->rx_len_errors++; |
|
|
2782 |
dev_kfree_skb(skb); |
1853 |
goto next_pkt; |
2783 |
goto next_pkt; |
1854 |
} |
2784 |
} |
1855 |
} |
2785 |
} |
1856 |
/* framing errors are soft errors */ |
2786 |
/* framing errors are soft errors */ |
1857 |
if (Flags & NV_RX2_FRAMINGERR) { |
2787 |
else if (Flags & NV_RX2_FRAMINGERR) { |
1858 |
if (Flags & NV_RX2_SUBSTRACT1) { |
2788 |
if (Flags & NV_RX2_SUBSTRACT1) { |
1859 |
len--; |
2789 |
len--; |
1860 |
} |
2790 |
} |
1861 |
} |
2791 |
} |
|
|
2792 |
/* the rest are hard errors */ |
2793 |
else { |
2794 |
dev_kfree_skb(skb); |
2795 |
goto next_pkt; |
2796 |
} |
1862 |
} |
2797 |
} |
1863 |
if (np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) { |
2798 |
|
1864 |
Flags &= NV_RX2_CHECKSUMMASK; |
2799 |
if (likely(np->rx_csum)) { |
1865 |
if (Flags == NV_RX2_CHECKSUMOK1 || |
2800 |
if (likely((Flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK2)) { |
1866 |
Flags == NV_RX2_CHECKSUMOK2 || |
2801 |
/*ip and tcp */ |
1867 |
Flags == NV_RX2_CHECKSUMOK3) { |
2802 |
skb->ip_summed = CHECKSUM_UNNECESSARY; |
1868 |
dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name); |
|
|
1869 |
np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY; |
1870 |
} else { |
2803 |
} else { |
1871 |
dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name); |
2804 |
if ((Flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK1 || |
|
|
2805 |
(Flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK3) { |
2806 |
skb->ip_summed = CHECKSUM_UNNECESSARY; |
2807 |
} |
1872 |
} |
2808 |
} |
1873 |
} |
2809 |
} |
1874 |
} |
2810 |
dprintk(KERN_DEBUG "%s: nv_rx_process_optimized:NVLAN rx done\n", dev->name); |
1875 |
/* got a valid packet - forward it to the network core */ |
|
|
1876 |
skb = np->rx_skbuff[i]; |
1877 |
np->rx_skbuff[i] = NULL; |
1878 |
|
2811 |
|
1879 |
skb_put(skb, len); |
2812 |
/* got a valid packet - forward it to the network core */ |
1880 |
skb->protocol = eth_type_trans(skb, dev); |
2813 |
skb_put(skb, len); |
1881 |
dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n", |
2814 |
skb->protocol = eth_type_trans(skb, dev); |
1882 |
dev->name, np->cur_rx, len, skb->protocol); |
2815 |
prefetch(skb->data); |
1883 |
if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT)) { |
2816 |
|
1884 |
vlan_hwaccel_rx(skb, np->vlangrp, vlanflags & NV_RX3_VLAN_TAG_MASK); |
2817 |
if (likely(!np->vlangrp)) { |
|
|
2818 |
netif_rx(skb); |
2819 |
} else { |
2820 |
vlanflags = le32_to_cpu(np->get_rx.ex->PacketBufferLow); |
2821 |
if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) |
2822 |
vlan_hwaccel_rx(skb, np->vlangrp, vlanflags & NV_RX3_VLAN_TAG_MASK); |
2823 |
else |
2824 |
netif_rx(skb); |
2825 |
} |
2826 |
|
2827 |
dev->last_rx = jiffies; |
2828 |
np->stats.rx_packets++; |
2829 |
np->stats.rx_bytes += len; |
1885 |
} else { |
2830 |
} else { |
1886 |
netif_rx(skb); |
2831 |
dev_kfree_skb(skb); |
1887 |
} |
2832 |
} |
1888 |
dev->last_rx = jiffies; |
|
|
1889 |
np->stats.rx_packets++; |
1890 |
np->stats.rx_bytes += len; |
1891 |
next_pkt: |
2833 |
next_pkt: |
1892 |
np->cur_rx++; |
2834 |
if (unlikely(np->get_rx.ex++ == np->last_rx.ex)) |
|
|
2835 |
np->get_rx.ex = np->first_rx.ex; |
2836 |
if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx)) |
2837 |
np->get_rx_ctx = np->first_rx_ctx; |
1893 |
} |
2838 |
} |
|
|
2839 |
return rx_processed_cnt; |
1894 |
} |
2840 |
} |
1895 |
|
2841 |
|
1896 |
static void set_bufsize(struct net_device *dev) |
2842 |
static void set_bufsize(struct net_device *dev) |
1897 |
{ |
2843 |
{ |
1898 |
struct fe_priv *np = netdev_priv(dev); |
2844 |
struct fe_priv *np = get_nvpriv(dev); |
1899 |
|
2845 |
|
1900 |
if (dev->mtu <= ETH_DATA_LEN) |
2846 |
if (dev->mtu <= ETH_DATA_LEN) |
1901 |
np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS; |
2847 |
np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS; |
Lines 1909-1915
Link Here
|
1909 |
*/ |
2855 |
*/ |
1910 |
static int nv_change_mtu(struct net_device *dev, int new_mtu) |
2856 |
static int nv_change_mtu(struct net_device *dev, int new_mtu) |
1911 |
{ |
2857 |
{ |
1912 |
struct fe_priv *np = netdev_priv(dev); |
2858 |
struct fe_priv *np = get_nvpriv(dev); |
1913 |
int old_mtu; |
2859 |
int old_mtu; |
1914 |
|
2860 |
|
1915 |
if (new_mtu < 64 || new_mtu > np->pkt_limit) |
2861 |
if (new_mtu < 64 || new_mtu > np->pkt_limit) |
Lines 1987-1998
Link Here
|
1987 |
*/ |
2933 |
*/ |
1988 |
static int nv_set_mac_address(struct net_device *dev, void *addr) |
2934 |
static int nv_set_mac_address(struct net_device *dev, void *addr) |
1989 |
{ |
2935 |
{ |
1990 |
struct fe_priv *np = netdev_priv(dev); |
2936 |
struct fe_priv *np = get_nvpriv(dev); |
1991 |
struct sockaddr *macaddr = (struct sockaddr*)addr; |
2937 |
struct sockaddr *macaddr = (struct sockaddr*)addr; |
1992 |
|
2938 |
|
1993 |
if(!is_valid_ether_addr(macaddr->sa_data)) |
2939 |
if(!is_valid_ether_addr(macaddr->sa_data)) |
1994 |
return -EADDRNOTAVAIL; |
2940 |
return -EADDRNOTAVAIL; |
1995 |
|
2941 |
|
|
|
2942 |
dprintk(KERN_DEBUG "%s: nv_set_mac_address \n", dev->name); |
1996 |
/* synchronized against open : rtnl_lock() held by caller */ |
2943 |
/* synchronized against open : rtnl_lock() held by caller */ |
1997 |
memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN); |
2944 |
memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN); |
1998 |
|
2945 |
|
Lines 2018-2028
Link Here
|
2018 |
|
2965 |
|
2019 |
/* |
2966 |
/* |
2020 |
* nv_set_multicast: dev->set_multicast function |
2967 |
* nv_set_multicast: dev->set_multicast function |
2021 |
* Called with netif_tx_lock held. |
2968 |
* Called with dev->xmit_lock held. |
2022 |
*/ |
2969 |
*/ |
2023 |
static void nv_set_multicast(struct net_device *dev) |
2970 |
static void nv_set_multicast(struct net_device *dev) |
2024 |
{ |
2971 |
{ |
2025 |
struct fe_priv *np = netdev_priv(dev); |
2972 |
struct fe_priv *np = get_nvpriv(dev); |
2026 |
u8 __iomem *base = get_hwbase(dev); |
2973 |
u8 __iomem *base = get_hwbase(dev); |
2027 |
u32 addr[2]; |
2974 |
u32 addr[2]; |
2028 |
u32 mask[2]; |
2975 |
u32 mask[2]; |
Lines 2032-2038
Link Here
|
2032 |
memset(mask, 0, sizeof(mask)); |
2979 |
memset(mask, 0, sizeof(mask)); |
2033 |
|
2980 |
|
2034 |
if (dev->flags & IFF_PROMISC) { |
2981 |
if (dev->flags & IFF_PROMISC) { |
2035 |
printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name); |
2982 |
dprintk(KERN_DEBUG "%s: Promiscuous mode enabled.\n", dev->name); |
2036 |
pff |= NVREG_PFF_PROMISC; |
2983 |
pff |= NVREG_PFF_PROMISC; |
2037 |
} else { |
2984 |
} else { |
2038 |
pff |= NVREG_PFF_MYADDR; |
2985 |
pff |= NVREG_PFF_MYADDR; |
Lines 2082-2088
Link Here
|
2082 |
|
3029 |
|
2083 |
static void nv_update_pause(struct net_device *dev, u32 pause_flags) |
3030 |
static void nv_update_pause(struct net_device *dev, u32 pause_flags) |
2084 |
{ |
3031 |
{ |
2085 |
struct fe_priv *np = netdev_priv(dev); |
3032 |
struct fe_priv *np = get_nvpriv(dev); |
2086 |
u8 __iomem *base = get_hwbase(dev); |
3033 |
u8 __iomem *base = get_hwbase(dev); |
2087 |
|
3034 |
|
2088 |
np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE); |
3035 |
np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE); |
Lines 2104-2110
Link Here
|
2104 |
np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; |
3051 |
np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; |
2105 |
} else { |
3052 |
} else { |
2106 |
writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); |
3053 |
writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); |
2107 |
writel(regmisc, base + NvRegMisc1); |
3054 |
writel(regmisc, base + NvRegMisc1); |
2108 |
} |
3055 |
} |
2109 |
} |
3056 |
} |
2110 |
} |
3057 |
} |
Lines 2122-2128
Link Here
|
2122 |
*/ |
3069 |
*/ |
2123 |
static int nv_update_linkspeed(struct net_device *dev) |
3070 |
static int nv_update_linkspeed(struct net_device *dev) |
2124 |
{ |
3071 |
{ |
2125 |
struct fe_priv *np = netdev_priv(dev); |
3072 |
struct fe_priv *np = get_nvpriv(dev); |
2126 |
u8 __iomem *base = get_hwbase(dev); |
3073 |
u8 __iomem *base = get_hwbase(dev); |
2127 |
int adv = 0; |
3074 |
int adv = 0; |
2128 |
int lpa = 0; |
3075 |
int lpa = 0; |
Lines 2148-2154
Link Here
|
2148 |
goto set_speed; |
3095 |
goto set_speed; |
2149 |
} |
3096 |
} |
2150 |
|
3097 |
|
2151 |
if (np->autoneg == 0) { |
3098 |
if (np->autoneg == AUTONEG_DISABLE) { |
2152 |
dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n", |
3099 |
dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n", |
2153 |
dev->name, np->fixed_mode); |
3100 |
dev->name, np->fixed_mode); |
2154 |
if (np->fixed_mode & LPA_100FULL) { |
3101 |
if (np->fixed_mode & LPA_100FULL) { |
Lines 2181-2187
Link Here
|
2181 |
lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); |
3128 |
lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); |
2182 |
dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n", |
3129 |
dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n", |
2183 |
dev->name, adv, lpa); |
3130 |
dev->name, adv, lpa); |
2184 |
|
|
|
2185 |
retval = 1; |
3131 |
retval = 1; |
2186 |
if (np->gigabit == PHY_GIGABIT) { |
3132 |
if (np->gigabit == PHY_GIGABIT) { |
2187 |
control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
3133 |
control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
Lines 2268-2274
Link Here
|
2268 |
txreg = NVREG_TX_WM_DESC2_3_DEFAULT; |
3214 |
txreg = NVREG_TX_WM_DESC2_3_DEFAULT; |
2269 |
} |
3215 |
} |
2270 |
writel(txreg, base + NvRegTxWatermark); |
3216 |
writel(txreg, base + NvRegTxWatermark); |
2271 |
|
|
|
2272 |
writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD), |
3217 |
writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD), |
2273 |
base + NvRegMisc1); |
3218 |
base + NvRegMisc1); |
2274 |
pci_push(base); |
3219 |
pci_push(base); |
Lines 2306-2312
Link Here
|
2306 |
if (lpa_pause == LPA_PAUSE_ASYM) |
3251 |
if (lpa_pause == LPA_PAUSE_ASYM) |
2307 |
{ |
3252 |
{ |
2308 |
pause_flags |= NV_PAUSEFRAME_RX_ENABLE; |
3253 |
pause_flags |= NV_PAUSEFRAME_RX_ENABLE; |
2309 |
} |
3254 |
} |
2310 |
break; |
3255 |
break; |
2311 |
} |
3256 |
} |
2312 |
} else { |
3257 |
} else { |
Lines 2352-2358
Link Here
|
2352 |
static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs) |
3297 |
static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs) |
2353 |
{ |
3298 |
{ |
2354 |
struct net_device *dev = (struct net_device *) data; |
3299 |
struct net_device *dev = (struct net_device *) data; |
2355 |
struct fe_priv *np = netdev_priv(dev); |
3300 |
struct fe_priv *np = get_nvpriv(dev); |
2356 |
u8 __iomem *base = get_hwbase(dev); |
3301 |
u8 __iomem *base = get_hwbase(dev); |
2357 |
u32 events; |
3302 |
u32 events; |
2358 |
int i; |
3303 |
int i; |
Lines 2372-2381
Link Here
|
2372 |
if (!(events & np->irqmask)) |
3317 |
if (!(events & np->irqmask)) |
2373 |
break; |
3318 |
break; |
2374 |
|
3319 |
|
2375 |
spin_lock(&np->lock); |
|
|
2376 |
nv_tx_done(dev); |
3320 |
nv_tx_done(dev); |
2377 |
spin_unlock(&np->lock); |
3321 |
|
2378 |
|
|
|
2379 |
nv_rx_process(dev); |
3322 |
nv_rx_process(dev); |
2380 |
if (nv_alloc_rx(dev)) { |
3323 |
if (nv_alloc_rx(dev)) { |
2381 |
spin_lock(&np->lock); |
3324 |
spin_lock(&np->lock); |
Lines 2383-2389
Link Here
|
2383 |
mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
3326 |
mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
2384 |
spin_unlock(&np->lock); |
3327 |
spin_unlock(&np->lock); |
2385 |
} |
3328 |
} |
2386 |
|
3329 |
|
2387 |
if (events & NVREG_IRQ_LINK) { |
3330 |
if (events & NVREG_IRQ_LINK) { |
2388 |
spin_lock(&np->lock); |
3331 |
spin_lock(&np->lock); |
2389 |
nv_link_irq(dev); |
3332 |
nv_link_irq(dev); |
Lines 2427-2436
Link Here
|
2427 |
return IRQ_RETVAL(i); |
3370 |
return IRQ_RETVAL(i); |
2428 |
} |
3371 |
} |
2429 |
|
3372 |
|
|
|
3373 |
#define TX_WORK_PER_LOOP 64 |
3374 |
#define RX_WORK_PER_LOOP 64 |
3375 |
static irqreturn_t nv_nic_irq_optimized(int foo, void *data, struct pt_regs *regs) |
3376 |
{ |
3377 |
struct net_device *dev = (struct net_device *) data; |
3378 |
struct fe_priv *np = get_nvpriv(dev); |
3379 |
u8 __iomem *base = get_hwbase(dev); |
3380 |
u32 events; |
3381 |
int i = 1; |
3382 |
|
3383 |
do { |
3384 |
if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
3385 |
events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; |
3386 |
writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
3387 |
} else { |
3388 |
events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; |
3389 |
writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); |
3390 |
} |
3391 |
if (events & np->irqmask) { |
3392 |
|
3393 |
nv_tx_done_optimized(dev, TX_WORK_PER_LOOP); |
3394 |
|
3395 |
if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) { |
3396 |
if (unlikely(nv_alloc_rx_optimized(dev))) { |
3397 |
spin_lock(&np->lock); |
3398 |
if (!np->in_shutdown) |
3399 |
mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
3400 |
spin_unlock(&np->lock); |
3401 |
} |
3402 |
} |
3403 |
if (unlikely(events & NVREG_IRQ_LINK)) { |
3404 |
spin_lock(&np->lock); |
3405 |
nv_link_irq(dev); |
3406 |
spin_unlock(&np->lock); |
3407 |
} |
3408 |
if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) { |
3409 |
spin_lock(&np->lock); |
3410 |
nv_linkchange(dev); |
3411 |
spin_unlock(&np->lock); |
3412 |
np->link_timeout = jiffies + LINK_TIMEOUT; |
3413 |
} |
3414 |
if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) { |
3415 |
spin_lock(&np->lock); |
3416 |
/* disable interrupts on the nic */ |
3417 |
if (!(np->msi_flags & NV_MSI_X_ENABLED)) |
3418 |
writel(0, base + NvRegIrqMask); |
3419 |
else |
3420 |
writel(np->irqmask, base + NvRegIrqMask); |
3421 |
pci_push(base); |
3422 |
|
3423 |
if (!np->in_shutdown) { |
3424 |
np->nic_poll_irq = np->irqmask; |
3425 |
np->recover_error = 1; |
3426 |
mod_timer(&np->nic_poll, jiffies + POLL_WAIT); |
3427 |
} |
3428 |
spin_unlock(&np->lock); |
3429 |
break; |
3430 |
} |
3431 |
} else |
3432 |
break; |
3433 |
} |
3434 |
while (i++ <= max_interrupt_work); |
3435 |
|
3436 |
return IRQ_RETVAL(i); |
3437 |
} |
3438 |
|
2430 |
static irqreturn_t nv_nic_irq_tx(int foo, void *data, struct pt_regs *regs) |
3439 |
static irqreturn_t nv_nic_irq_tx(int foo, void *data, struct pt_regs *regs) |
2431 |
{ |
3440 |
{ |
2432 |
struct net_device *dev = (struct net_device *) data; |
3441 |
struct net_device *dev = (struct net_device *) data; |
2433 |
struct fe_priv *np = netdev_priv(dev); |
3442 |
struct fe_priv *np = get_nvpriv(dev); |
2434 |
u8 __iomem *base = get_hwbase(dev); |
3443 |
u8 __iomem *base = get_hwbase(dev); |
2435 |
u32 events; |
3444 |
u32 events; |
2436 |
int i; |
3445 |
int i; |
Lines 2440-2454
Link Here
|
2440 |
for (i=0; ; i++) { |
3449 |
for (i=0; ; i++) { |
2441 |
events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL; |
3450 |
events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL; |
2442 |
writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus); |
3451 |
writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus); |
2443 |
pci_push(base); |
|
|
2444 |
dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events); |
3452 |
dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events); |
2445 |
if (!(events & np->irqmask)) |
3453 |
if (!(events & np->irqmask)) |
2446 |
break; |
3454 |
break; |
2447 |
|
3455 |
|
2448 |
spin_lock_irq(&np->lock); |
3456 |
nv_tx_done_optimized(dev, TX_WORK_PER_LOOP); |
2449 |
nv_tx_done(dev); |
3457 |
|
2450 |
spin_unlock_irq(&np->lock); |
|
|
2451 |
|
2452 |
if (events & (NVREG_IRQ_TX_ERR)) { |
3458 |
if (events & (NVREG_IRQ_TX_ERR)) { |
2453 |
dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n", |
3459 |
dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n", |
2454 |
dev->name, events); |
3460 |
dev->name, events); |
Lines 2477-2483
Link Here
|
2477 |
static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs) |
3483 |
static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs) |
2478 |
{ |
3484 |
{ |
2479 |
struct net_device *dev = (struct net_device *) data; |
3485 |
struct net_device *dev = (struct net_device *) data; |
2480 |
struct fe_priv *np = netdev_priv(dev); |
3486 |
struct fe_priv *np = get_nvpriv(dev); |
2481 |
u8 __iomem *base = get_hwbase(dev); |
3487 |
u8 __iomem *base = get_hwbase(dev); |
2482 |
u32 events; |
3488 |
u32 events; |
2483 |
int i; |
3489 |
int i; |
Lines 2487-2505
Link Here
|
2487 |
for (i=0; ; i++) { |
3493 |
for (i=0; ; i++) { |
2488 |
events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; |
3494 |
events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; |
2489 |
writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus); |
3495 |
writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus); |
2490 |
pci_push(base); |
|
|
2491 |
dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events); |
3496 |
dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events); |
2492 |
if (!(events & np->irqmask)) |
3497 |
if (!(events & np->irqmask)) |
2493 |
break; |
3498 |
break; |
2494 |
|
3499 |
|
2495 |
nv_rx_process(dev); |
3500 |
if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) { |
2496 |
if (nv_alloc_rx(dev)) { |
3501 |
if (unlikely(nv_alloc_rx_optimized(dev))) { |
2497 |
spin_lock_irq(&np->lock); |
3502 |
spin_lock_irq(&np->lock); |
2498 |
if (!np->in_shutdown) |
3503 |
if (!np->in_shutdown) |
2499 |
mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
3504 |
mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
2500 |
spin_unlock_irq(&np->lock); |
3505 |
spin_unlock_irq(&np->lock); |
|
|
3506 |
} |
2501 |
} |
3507 |
} |
2502 |
|
3508 |
|
2503 |
if (i > max_interrupt_work) { |
3509 |
if (i > max_interrupt_work) { |
2504 |
spin_lock_irq(&np->lock); |
3510 |
spin_lock_irq(&np->lock); |
2505 |
/* disable interrupts on the nic */ |
3511 |
/* disable interrupts on the nic */ |
Lines 2524-2530
Link Here
|
2524 |
static irqreturn_t nv_nic_irq_other(int foo, void *data, struct pt_regs *regs) |
3530 |
static irqreturn_t nv_nic_irq_other(int foo, void *data, struct pt_regs *regs) |
2525 |
{ |
3531 |
{ |
2526 |
struct net_device *dev = (struct net_device *) data; |
3532 |
struct net_device *dev = (struct net_device *) data; |
2527 |
struct fe_priv *np = netdev_priv(dev); |
3533 |
struct fe_priv *np = get_nvpriv(dev); |
2528 |
u8 __iomem *base = get_hwbase(dev); |
3534 |
u8 __iomem *base = get_hwbase(dev); |
2529 |
u32 events; |
3535 |
u32 events; |
2530 |
int i; |
3536 |
int i; |
Lines 2534-2544
Link Here
|
2534 |
for (i=0; ; i++) { |
3540 |
for (i=0; ; i++) { |
2535 |
events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER; |
3541 |
events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER; |
2536 |
writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus); |
3542 |
writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus); |
2537 |
pci_push(base); |
|
|
2538 |
dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); |
3543 |
dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); |
2539 |
if (!(events & np->irqmask)) |
3544 |
if (!(events & np->irqmask)) |
2540 |
break; |
3545 |
break; |
2541 |
|
3546 |
|
2542 |
if (events & NVREG_IRQ_LINK) { |
3547 |
if (events & NVREG_IRQ_LINK) { |
2543 |
spin_lock_irq(&np->lock); |
3548 |
spin_lock_irq(&np->lock); |
2544 |
nv_link_irq(dev); |
3549 |
nv_link_irq(dev); |
Lines 2550-2555
Link Here
|
2550 |
spin_unlock_irq(&np->lock); |
3555 |
spin_unlock_irq(&np->lock); |
2551 |
np->link_timeout = jiffies + LINK_TIMEOUT; |
3556 |
np->link_timeout = jiffies + LINK_TIMEOUT; |
2552 |
} |
3557 |
} |
|
|
3558 |
if (events & NVREG_IRQ_RECOVER_ERROR) { |
3559 |
spin_lock_irq(&np->lock); |
3560 |
/* disable interrupts on the nic */ |
3561 |
writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); |
3562 |
pci_push(base); |
3563 |
|
3564 |
if (!np->in_shutdown) { |
3565 |
np->nic_poll_irq |= NVREG_IRQ_OTHER; |
3566 |
np->recover_error = 1; |
3567 |
mod_timer(&np->nic_poll, jiffies + POLL_WAIT); |
3568 |
} |
3569 |
spin_unlock_irq(&np->lock); |
3570 |
break; |
3571 |
} |
2553 |
if (events & (NVREG_IRQ_UNKNOWN)) { |
3572 |
if (events & (NVREG_IRQ_UNKNOWN)) { |
2554 |
printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n", |
3573 |
printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n", |
2555 |
dev->name, events); |
3574 |
dev->name, events); |
Lines 2578-2584
Link Here
|
2578 |
static irqreturn_t nv_nic_irq_test(int foo, void *data, struct pt_regs *regs) |
3597 |
static irqreturn_t nv_nic_irq_test(int foo, void *data, struct pt_regs *regs) |
2579 |
{ |
3598 |
{ |
2580 |
struct net_device *dev = (struct net_device *) data; |
3599 |
struct net_device *dev = (struct net_device *) data; |
2581 |
struct fe_priv *np = netdev_priv(dev); |
3600 |
struct fe_priv *np = get_nvpriv(dev); |
2582 |
u8 __iomem *base = get_hwbase(dev); |
3601 |
u8 __iomem *base = get_hwbase(dev); |
2583 |
u32 events; |
3602 |
u32 events; |
2584 |
|
3603 |
|
Lines 2595-2610
Link Here
|
2595 |
dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); |
3614 |
dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events); |
2596 |
if (!(events & NVREG_IRQ_TIMER)) |
3615 |
if (!(events & NVREG_IRQ_TIMER)) |
2597 |
return IRQ_RETVAL(0); |
3616 |
return IRQ_RETVAL(0); |
2598 |
|
3617 |
|
2599 |
spin_lock(&np->lock); |
3618 |
spin_lock(&np->lock); |
2600 |
np->intr_test = 1; |
3619 |
np->intr_test = 1; |
2601 |
spin_unlock(&np->lock); |
3620 |
spin_unlock(&np->lock); |
2602 |
|
3621 |
|
2603 |
dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name); |
3622 |
dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name); |
2604 |
|
3623 |
|
2605 |
return IRQ_RETVAL(1); |
3624 |
return IRQ_RETVAL(1); |
2606 |
} |
3625 |
} |
2607 |
|
3626 |
|
|
|
3627 |
#ifdef CONFIG_PCI_MSI |
2608 |
static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask) |
3628 |
static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask) |
2609 |
{ |
3629 |
{ |
2610 |
u8 __iomem *base = get_hwbase(dev); |
3630 |
u8 __iomem *base = get_hwbase(dev); |
Lines 2630-2641
Link Here
|
2630 |
} |
3650 |
} |
2631 |
writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1); |
3651 |
writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1); |
2632 |
} |
3652 |
} |
|
|
3653 |
#endif |
2633 |
|
3654 |
|
2634 |
static int nv_request_irq(struct net_device *dev, int intr_test) |
3655 |
static int nv_request_irq(struct net_device *dev, int intr_test) |
2635 |
{ |
3656 |
{ |
2636 |
struct fe_priv *np = get_nvpriv(dev); |
3657 |
struct fe_priv *np = get_nvpriv(dev); |
2637 |
u8 __iomem *base = get_hwbase(dev); |
|
|
2638 |
int ret = 1; |
3658 |
int ret = 1; |
|
|
3659 |
|
3660 |
#if NVVER > SLES9 |
3661 |
u8 __iomem *base = get_hwbase(dev); |
2639 |
int i; |
3662 |
int i; |
2640 |
|
3663 |
|
2641 |
if (np->msi_flags & NV_MSI_X_CAPABLE) { |
3664 |
if (np->msi_flags & NV_MSI_X_CAPABLE) { |
Lines 2646-2666
Link Here
|
2646 |
np->msi_flags |= NV_MSI_X_ENABLED; |
3669 |
np->msi_flags |= NV_MSI_X_ENABLED; |
2647 |
if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) { |
3670 |
if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) { |
2648 |
/* Request irq for rx handling */ |
3671 |
/* Request irq for rx handling */ |
2649 |
if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) { |
3672 |
if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, SA_SHIRQ, dev->name, dev) != 0) { |
2650 |
printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret); |
3673 |
printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret); |
2651 |
pci_disable_msix(np->pci_dev); |
3674 |
pci_disable_msix(np->pci_dev); |
2652 |
np->msi_flags &= ~NV_MSI_X_ENABLED; |
3675 |
np->msi_flags &= ~NV_MSI_X_ENABLED; |
2653 |
goto out_err; |
3676 |
goto out_err; |
2654 |
} |
3677 |
} |
2655 |
/* Request irq for tx handling */ |
3678 |
/* Request irq for tx handling */ |
2656 |
if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) { |
3679 |
if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, SA_SHIRQ, dev->name, dev) != 0) { |
2657 |
printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret); |
3680 |
printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret); |
2658 |
pci_disable_msix(np->pci_dev); |
3681 |
pci_disable_msix(np->pci_dev); |
2659 |
np->msi_flags &= ~NV_MSI_X_ENABLED; |
3682 |
np->msi_flags &= ~NV_MSI_X_ENABLED; |
2660 |
goto out_free_rx; |
3683 |
goto out_free_rx; |
2661 |
} |
3684 |
} |
2662 |
/* Request irq for link and timer handling */ |
3685 |
/* Request irq for link and timer handling */ |
2663 |
if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) { |
3686 |
if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, SA_SHIRQ, dev->name, dev) != 0) { |
2664 |
printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret); |
3687 |
printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret); |
2665 |
pci_disable_msix(np->pci_dev); |
3688 |
pci_disable_msix(np->pci_dev); |
2666 |
np->msi_flags &= ~NV_MSI_X_ENABLED; |
3689 |
np->msi_flags &= ~NV_MSI_X_ENABLED; |
Lines 2669-2683
Link Here
|
2669 |
/* map interrupts to their respective vector */ |
3692 |
/* map interrupts to their respective vector */ |
2670 |
writel(0, base + NvRegMSIXMap0); |
3693 |
writel(0, base + NvRegMSIXMap0); |
2671 |
writel(0, base + NvRegMSIXMap1); |
3694 |
writel(0, base + NvRegMSIXMap1); |
|
|
3695 |
#ifdef CONFIG_PCI_MSI |
2672 |
set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL); |
3696 |
set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL); |
2673 |
set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL); |
3697 |
set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL); |
2674 |
set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER); |
3698 |
set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER); |
|
|
3699 |
#endif |
2675 |
} else { |
3700 |
} else { |
2676 |
/* Request irq for all interrupts */ |
3701 |
/* Request irq for all interrupts */ |
2677 |
if ((!intr_test && |
3702 |
if ((!intr_test && np->desc_ver == DESC_VER_3 && |
2678 |
request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) || |
3703 |
request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_optimized, SA_SHIRQ, dev->name, dev) != 0) || |
|
|
3704 |
(!intr_test && np->desc_ver != DESC_VER_3 && |
3705 |
request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) || |
2679 |
(intr_test && |
3706 |
(intr_test && |
2680 |
request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) { |
3707 |
request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, SA_SHIRQ, dev->name, dev) != 0)) { |
2681 |
printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); |
3708 |
printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); |
2682 |
pci_disable_msix(np->pci_dev); |
3709 |
pci_disable_msix(np->pci_dev); |
2683 |
np->msi_flags &= ~NV_MSI_X_ENABLED; |
3710 |
np->msi_flags &= ~NV_MSI_X_ENABLED; |
Lines 2693-2700
Link Here
|
2693 |
if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) { |
3720 |
if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) { |
2694 |
if ((ret = pci_enable_msi(np->pci_dev)) == 0) { |
3721 |
if ((ret = pci_enable_msi(np->pci_dev)) == 0) { |
2695 |
np->msi_flags |= NV_MSI_ENABLED; |
3722 |
np->msi_flags |= NV_MSI_ENABLED; |
2696 |
if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) || |
3723 |
if ((!intr_test && np->desc_ver == DESC_VER_3 && |
2697 |
(intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) { |
3724 |
request_irq(np->pci_dev->irq, &nv_nic_irq_optimized, SA_SHIRQ, dev->name, dev) != 0) || |
|
|
3725 |
(!intr_test && np->desc_ver != DESC_VER_3 && |
3726 |
request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) || |
3727 |
(intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, SA_SHIRQ, dev->name, dev) != 0)) { |
3728 |
printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); |
3729 |
pci_disable_msi(np->pci_dev); |
3730 |
np->msi_flags &= ~NV_MSI_ENABLED; |
3731 |
goto out_err; |
3732 |
} |
3733 |
|
3734 |
/* map interrupts to vector 0 */ |
3735 |
writel(0, base + NvRegMSIMap0); |
3736 |
writel(0, base + NvRegMSIMap1); |
3737 |
/* enable msi vector 0 */ |
3738 |
writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); |
3739 |
} |
3740 |
} |
3741 |
#else |
3742 |
#ifdef CONFIG_PCI_MSI |
3743 |
u8 __iomem *base = get_hwbase(dev); |
3744 |
int i; |
3745 |
|
3746 |
if (np->msi_flags & NV_MSI_X_CAPABLE) { |
3747 |
for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) { |
3748 |
np->msi_x_entry[i].entry = i; |
3749 |
} |
3750 |
if ((ret = pci_enable_msi(np->pci_dev)) == 0) { |
3751 |
np->msi_flags |= NV_MSI_X_ENABLED; |
3752 |
if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) { |
3753 |
msi_alloc_vectors(np->pci_dev,(int *)np->msi_x_entry,2); |
3754 |
/* Request irq for rx handling */ |
3755 |
if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, SA_SHIRQ, dev->name, dev) != 0) { |
3756 |
printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret); |
3757 |
pci_disable_msi(np->pci_dev); |
3758 |
np->msi_flags &= ~NV_MSI_X_ENABLED; |
3759 |
goto out_err; |
3760 |
} |
3761 |
/* Request irq for tx handling */ |
3762 |
if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, SA_SHIRQ, dev->name, dev) != 0) { |
3763 |
printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret); |
3764 |
pci_disable_msi(np->pci_dev); |
3765 |
np->msi_flags &= ~NV_MSI_X_ENABLED; |
3766 |
goto out_free_rx; |
3767 |
} |
3768 |
/* Request irq for link and timer handling */ |
3769 |
if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, SA_SHIRQ, dev->name, dev) != 0) { |
3770 |
printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret); |
3771 |
pci_disable_msi(np->pci_dev); |
3772 |
np->msi_flags &= ~NV_MSI_X_ENABLED; |
3773 |
goto out_free_tx; |
3774 |
} |
3775 |
/* map interrupts to their respective vector */ |
3776 |
writel(0, base + NvRegMSIXMap0); |
3777 |
writel(0, base + NvRegMSIXMap1); |
3778 |
#ifdef CONFIG_PCI_MSI |
3779 |
set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL); |
3780 |
set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL); |
3781 |
set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER); |
3782 |
#endif |
3783 |
} else { |
3784 |
/* Request irq for all interrupts */ |
3785 |
if ((!intr_test && np->desc_ver == DESC_VER_3 && |
3786 |
request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_optimized, SA_SHIRQ, dev->name, dev) != 0) || |
3787 |
(!intr_test && np->desc_ver != DESC_VER_3 && |
3788 |
request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) || |
3789 |
(intr_test && |
3790 |
request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, SA_SHIRQ, dev->name, dev) != 0)) { |
3791 |
printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); |
3792 |
pci_disable_msi(np->pci_dev); |
3793 |
np->msi_flags &= ~NV_MSI_X_ENABLED; |
3794 |
goto out_err; |
3795 |
} |
3796 |
|
3797 |
/* map interrupts to vector 0 */ |
3798 |
writel(0, base + NvRegMSIXMap0); |
3799 |
writel(0, base + NvRegMSIXMap1); |
3800 |
} |
3801 |
} |
3802 |
} |
3803 |
if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) { |
3804 |
|
3805 |
if ((ret = pci_enable_msi(np->pci_dev)) == 0) { |
3806 |
np->msi_flags |= NV_MSI_ENABLED; |
3807 |
if ((!intr_test && np->desc_ver == DESC_VER_3 && |
3808 |
request_irq(np->pci_dev->irq, &nv_nic_irq_optimized, SA_SHIRQ, dev->name, dev) != 0) || |
3809 |
(!intr_test && np->desc_ver != DESC_VER_3 && |
3810 |
request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) || |
3811 |
(intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, SA_SHIRQ, dev->name, dev) != 0)) { |
2698 |
printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); |
3812 |
printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); |
2699 |
pci_disable_msi(np->pci_dev); |
3813 |
pci_disable_msi(np->pci_dev); |
2700 |
np->msi_flags &= ~NV_MSI_ENABLED; |
3814 |
np->msi_flags &= ~NV_MSI_ENABLED; |
Lines 2708-2734
Link Here
|
2708 |
writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); |
3822 |
writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); |
2709 |
} |
3823 |
} |
2710 |
} |
3824 |
} |
|
|
3825 |
#endif |
3826 |
#endif |
2711 |
if (ret != 0) { |
3827 |
if (ret != 0) { |
2712 |
if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) || |
3828 |
if ((!intr_test && np->desc_ver == DESC_VER_3 && |
2713 |
(intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) |
3829 |
request_irq(np->pci_dev->irq, &nv_nic_irq_optimized, SA_SHIRQ, dev->name, dev) != 0) || |
|
|
3830 |
(!intr_test && np->desc_ver != DESC_VER_3 && |
3831 |
request_irq(np->pci_dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev) != 0) || |
3832 |
(intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, SA_SHIRQ, dev->name, dev) != 0)) |
2714 |
goto out_err; |
3833 |
goto out_err; |
2715 |
|
3834 |
|
2716 |
} |
3835 |
} |
2717 |
|
3836 |
|
2718 |
return 0; |
3837 |
return 0; |
|
|
3838 |
|
3839 |
#if NVVER > SLES9 |
3840 |
out_free_tx: |
3841 |
free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev); |
3842 |
out_free_rx: |
3843 |
free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev); |
3844 |
#else |
3845 |
#ifdef CONFIG_PCI_MSI |
2719 |
out_free_tx: |
3846 |
out_free_tx: |
2720 |
free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev); |
3847 |
free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev); |
2721 |
out_free_rx: |
3848 |
out_free_rx: |
2722 |
free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev); |
3849 |
free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev); |
|
|
3850 |
#endif |
3851 |
#endif |
2723 |
out_err: |
3852 |
out_err: |
2724 |
return 1; |
3853 |
return 1; |
2725 |
} |
3854 |
} |
2726 |
|
3855 |
|
|
|
3856 |
#if NVVER > SLES9 |
2727 |
static void nv_free_irq(struct net_device *dev) |
3857 |
static void nv_free_irq(struct net_device *dev) |
2728 |
{ |
3858 |
{ |
2729 |
struct fe_priv *np = get_nvpriv(dev); |
3859 |
struct fe_priv *np = get_nvpriv(dev); |
2730 |
int i; |
3860 |
int i; |
2731 |
|
3861 |
|
2732 |
if (np->msi_flags & NV_MSI_X_ENABLED) { |
3862 |
if (np->msi_flags & NV_MSI_X_ENABLED) { |
2733 |
for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) { |
3863 |
for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) { |
2734 |
free_irq(np->msi_x_entry[i].vector, dev); |
3864 |
free_irq(np->msi_x_entry[i].vector, dev); |
Lines 2743-2753
Link Here
|
2743 |
} |
3873 |
} |
2744 |
} |
3874 |
} |
2745 |
} |
3875 |
} |
|
|
3876 |
#else |
3877 |
static void nv_free_irq(struct net_device *dev) |
3878 |
{ |
3879 |
struct fe_priv *np = get_nvpriv(dev); |
3880 |
|
3881 |
#ifdef CONFIG_PCI_MSI |
3882 |
int i; |
3883 |
|
3884 |
if (np->msi_flags & NV_MSI_X_ENABLED) { |
3885 |
for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) { |
3886 |
free_irq(np->msi_x_entry[i].vector, dev); |
3887 |
} |
3888 |
pci_disable_msi(np->pci_dev); |
3889 |
np->msi_flags &= ~NV_MSI_X_ENABLED; |
3890 |
} else { |
3891 |
free_irq(np->pci_dev->irq, dev); |
3892 |
|
3893 |
if (np->msi_flags & NV_MSI_ENABLED) { |
3894 |
pci_disable_msi(np->pci_dev); |
3895 |
np->msi_flags &= ~NV_MSI_ENABLED; |
3896 |
} |
3897 |
} |
3898 |
#else |
3899 |
free_irq(np->pci_dev->irq, dev); |
3900 |
#endif |
3901 |
|
3902 |
} |
3903 |
#endif |
2746 |
|
3904 |
|
2747 |
static void nv_do_nic_poll(unsigned long data) |
3905 |
static void nv_do_nic_poll(unsigned long data) |
2748 |
{ |
3906 |
{ |
2749 |
struct net_device *dev = (struct net_device *) data; |
3907 |
struct net_device *dev = (struct net_device *) data; |
2750 |
struct fe_priv *np = netdev_priv(dev); |
3908 |
struct fe_priv *np = get_nvpriv(dev); |
2751 |
u8 __iomem *base = get_hwbase(dev); |
3909 |
u8 __iomem *base = get_hwbase(dev); |
2752 |
u32 mask = 0; |
3910 |
u32 mask = 0; |
2753 |
|
3911 |
|
Lines 2757-2871
Link Here
|
2757 |
* nv_nic_irq because that may decide to do otherwise |
3915 |
* nv_nic_irq because that may decide to do otherwise |
2758 |
*/ |
3916 |
*/ |
2759 |
|
3917 |
|
2760 |
if (!using_multi_irqs(dev)) { |
3918 |
if (!using_multi_irqs(dev)) { |
2761 |
if (np->msi_flags & NV_MSI_X_ENABLED) |
3919 |
if (np->msi_flags & NV_MSI_X_ENABLED) |
2762 |
disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
3920 |
disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
2763 |
else |
3921 |
else |
2764 |
disable_irq_lockdep(dev->irq); |
3922 |
disable_irq(dev->irq); |
2765 |
mask = np->irqmask; |
3923 |
mask = np->irqmask; |
2766 |
} else { |
3924 |
} else { |
2767 |
if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { |
3925 |
if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { |
2768 |
disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
3926 |
disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
2769 |
mask |= NVREG_IRQ_RX_ALL; |
3927 |
mask |= NVREG_IRQ_RX_ALL; |
2770 |
} |
3928 |
} |
2771 |
if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { |
3929 |
if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { |
2772 |
disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
3930 |
disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
2773 |
mask |= NVREG_IRQ_TX_ALL; |
3931 |
mask |= NVREG_IRQ_TX_ALL; |
2774 |
} |
3932 |
} |
2775 |
if (np->nic_poll_irq & NVREG_IRQ_OTHER) { |
3933 |
if (np->nic_poll_irq & NVREG_IRQ_OTHER) { |
2776 |
disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
3934 |
disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
2777 |
mask |= NVREG_IRQ_OTHER; |
3935 |
mask |= NVREG_IRQ_OTHER; |
|
|
3936 |
} |
3937 |
} |
3938 |
np->nic_poll_irq = 0; |
3939 |
|
3940 |
if (np->recover_error) { |
3941 |
np->recover_error = 0; |
3942 |
printk(KERN_INFO "forcedeth: MAC in recoverable error state\n"); |
3943 |
if (netif_running(dev)) { |
3944 |
netif_tx_lock_bh(dev); |
3945 |
spin_lock(&np->lock); |
3946 |
/* stop engines */ |
3947 |
nv_stop_rx(dev); |
3948 |
nv_stop_tx(dev); |
3949 |
nv_txrx_reset(dev); |
3950 |
/* drain rx queue */ |
3951 |
nv_drain_rx(dev); |
3952 |
nv_drain_tx(dev); |
3953 |
/* reinit driver view of the rx queue */ |
3954 |
set_bufsize(dev); |
3955 |
if (nv_init_ring(dev)) { |
3956 |
if (!np->in_shutdown) |
3957 |
mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
3958 |
} |
3959 |
/* reinit nic view of the rx queue */ |
3960 |
writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
3961 |
setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
3962 |
writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
3963 |
base + NvRegRingSizes); |
3964 |
pci_push(base); |
3965 |
writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
3966 |
pci_push(base); |
3967 |
|
3968 |
/* restart rx engine */ |
3969 |
nv_start_rx(dev); |
3970 |
nv_start_tx(dev); |
3971 |
spin_unlock(&np->lock); |
3972 |
netif_tx_unlock_bh(dev); |
2778 |
} |
3973 |
} |
2779 |
} |
3974 |
} |
2780 |
np->nic_poll_irq = 0; |
|
|
2781 |
|
2782 |
/* FIXME: Do we need synchronize_irq(dev->irq) here? */ |
3975 |
/* FIXME: Do we need synchronize_irq(dev->irq) here? */ |
2783 |
|
3976 |
|
2784 |
writel(mask, base + NvRegIrqMask); |
3977 |
writel(mask, base + NvRegIrqMask); |
2785 |
pci_push(base); |
3978 |
pci_push(base); |
2786 |
|
3979 |
|
2787 |
if (!using_multi_irqs(dev)) { |
3980 |
if (!using_multi_irqs(dev)) { |
2788 |
nv_nic_irq(0, dev, NULL); |
3981 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
|
3982 |
nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL); |
3983 |
else |
3984 |
nv_nic_irq_optimized((int) 0, (void *) data, (struct pt_regs *) NULL); |
2789 |
if (np->msi_flags & NV_MSI_X_ENABLED) |
3985 |
if (np->msi_flags & NV_MSI_X_ENABLED) |
2790 |
enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
3986 |
enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); |
2791 |
else |
3987 |
else |
2792 |
enable_irq_lockdep(dev->irq); |
3988 |
enable_irq(dev->irq); |
2793 |
} else { |
3989 |
} else { |
2794 |
if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { |
3990 |
if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { |
2795 |
nv_nic_irq_rx(0, dev, NULL); |
3991 |
nv_nic_irq_rx((int) 0, (void *) data, (struct pt_regs *) NULL); |
2796 |
enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
3992 |
enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); |
2797 |
} |
3993 |
} |
2798 |
if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { |
3994 |
if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { |
2799 |
nv_nic_irq_tx(0, dev, NULL); |
3995 |
nv_nic_irq_tx((int) 0, (void *) data, (struct pt_regs *) NULL); |
2800 |
enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
3996 |
enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); |
2801 |
} |
3997 |
} |
2802 |
if (np->nic_poll_irq & NVREG_IRQ_OTHER) { |
3998 |
if (np->nic_poll_irq & NVREG_IRQ_OTHER) { |
2803 |
nv_nic_irq_other(0, dev, NULL); |
3999 |
nv_nic_irq_other((int) 0, (void *) data, (struct pt_regs *) NULL); |
2804 |
enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
4000 |
enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); |
2805 |
} |
4001 |
} |
2806 |
} |
4002 |
} |
2807 |
} |
4003 |
} |
2808 |
|
4004 |
|
|
|
4005 |
#if NVVER > RHES3 |
2809 |
#ifdef CONFIG_NET_POLL_CONTROLLER |
4006 |
#ifdef CONFIG_NET_POLL_CONTROLLER |
2810 |
static void nv_poll_controller(struct net_device *dev) |
4007 |
static void nv_poll_controller(struct net_device *dev) |
2811 |
{ |
4008 |
{ |
2812 |
nv_do_nic_poll((unsigned long) dev); |
4009 |
nv_do_nic_poll((unsigned long) dev); |
2813 |
} |
4010 |
} |
2814 |
#endif |
4011 |
#endif |
|
|
4012 |
#else |
4013 |
static void nv_poll_controller(struct net_device *dev) |
4014 |
{ |
4015 |
nv_do_nic_poll((unsigned long) dev); |
4016 |
} |
4017 |
#endif |
2815 |
|
4018 |
|
2816 |
static void nv_do_stats_poll(unsigned long data) |
4019 |
static void nv_do_stats_poll(unsigned long data) |
2817 |
{ |
4020 |
{ |
2818 |
struct net_device *dev = (struct net_device *) data; |
4021 |
struct net_device *dev = (struct net_device *) data; |
2819 |
struct fe_priv *np = netdev_priv(dev); |
4022 |
struct fe_priv *np = get_nvpriv(dev); |
2820 |
u8 __iomem *base = get_hwbase(dev); |
4023 |
u8 __iomem *base = get_hwbase(dev); |
2821 |
|
4024 |
|
2822 |
np->estats.tx_bytes += readl(base + NvRegTxCnt); |
4025 |
spin_lock_irq(&np->lock); |
2823 |
np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt); |
4026 |
|
2824 |
np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt); |
4027 |
np->estats.tx_dropped = np->stats.tx_dropped; |
2825 |
np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt); |
4028 |
if (np->driver_data & DEV_HAS_STATISTICS) { |
2826 |
np->estats.tx_late_collision += readl(base + NvRegTxLateCol); |
4029 |
np->estats.tx_packets += readl(base + NvRegTxFrame); |
2827 |
np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow); |
4030 |
np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow); |
2828 |
np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier); |
4031 |
np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier); |
2829 |
np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef); |
4032 |
np->estats.tx_bytes += readl(base + NvRegTxCnt); |
2830 |
np->estats.tx_retry_error += readl(base + NvRegTxRetryErr); |
4033 |
np->estats.rx_bytes += readl(base + NvRegRxCnt); |
2831 |
np->estats.tx_deferral += readl(base + NvRegTxDef); |
4034 |
np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr); |
2832 |
np->estats.tx_packets += readl(base + NvRegTxFrame); |
4035 |
np->estats.rx_over_errors += readl(base + NvRegRxOverflow); |
2833 |
np->estats.tx_pause += readl(base + NvRegTxPause); |
4036 |
|
2834 |
np->estats.rx_frame_error += readl(base + NvRegRxFrameErr); |
4037 |
np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt); |
2835 |
np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte); |
4038 |
np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt); |
2836 |
np->estats.rx_late_collision += readl(base + NvRegRxLateCol); |
4039 |
np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt); |
2837 |
np->estats.rx_runt += readl(base + NvRegRxRunt); |
4040 |
np->estats.tx_late_collision += readl(base + NvRegTxLateCol); |
2838 |
np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong); |
4041 |
np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef); |
2839 |
np->estats.rx_over_errors += readl(base + NvRegRxOverflow); |
4042 |
np->estats.tx_retry_error += readl(base + NvRegTxRetryErr); |
2840 |
np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr); |
4043 |
np->estats.rx_frame_error += readl(base + NvRegRxFrameErr); |
2841 |
np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr); |
4044 |
np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte); |
2842 |
np->estats.rx_length_error += readl(base + NvRegRxLenErr); |
4045 |
np->estats.rx_late_collision += readl(base + NvRegRxLateCol); |
2843 |
np->estats.rx_unicast += readl(base + NvRegRxUnicast); |
4046 |
np->estats.rx_runt += readl(base + NvRegRxRunt); |
2844 |
np->estats.rx_multicast += readl(base + NvRegRxMulticast); |
4047 |
np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong); |
2845 |
np->estats.rx_broadcast += readl(base + NvRegRxBroadcast); |
4048 |
np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr); |
2846 |
np->estats.rx_bytes += readl(base + NvRegRxCnt); |
4049 |
np->estats.rx_length_error += readl(base + NvRegRxLenErr); |
2847 |
np->estats.rx_pause += readl(base + NvRegRxPause); |
4050 |
np->estats.rx_unicast += readl(base + NvRegRxUnicast); |
2848 |
np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame); |
4051 |
np->estats.rx_multicast += readl(base + NvRegRxMulticast); |
2849 |
np->estats.rx_packets = |
4052 |
np->estats.rx_broadcast += readl(base + NvRegRxBroadcast); |
2850 |
np->estats.rx_unicast + |
4053 |
np->estats.tx_deferral += readl(base + NvRegTxDef); |
2851 |
np->estats.rx_multicast + |
4054 |
np->estats.tx_pause += readl(base + NvRegTxPause); |
2852 |
np->estats.rx_broadcast; |
4055 |
np->estats.rx_pause += readl(base + NvRegRxPause); |
2853 |
np->estats.rx_errors_total = |
4056 |
np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame); |
2854 |
np->estats.rx_crc_errors + |
4057 |
np->estats.rx_packets = |
2855 |
np->estats.rx_over_errors + |
4058 |
np->estats.rx_unicast + |
2856 |
np->estats.rx_frame_error + |
4059 |
np->estats.rx_multicast + |
2857 |
(np->estats.rx_frame_align_error - np->estats.rx_extra_byte) + |
4060 |
np->estats.rx_broadcast; |
2858 |
np->estats.rx_late_collision + |
4061 |
np->estats.rx_errors_total = |
2859 |
np->estats.rx_runt + |
4062 |
np->estats.rx_crc_errors + |
2860 |
np->estats.rx_frame_too_long; |
4063 |
np->estats.rx_over_errors + |
|
|
4064 |
np->estats.rx_frame_error + |
4065 |
(np->estats.rx_frame_align_error - np->estats.rx_extra_byte) + |
4066 |
np->estats.rx_late_collision + |
4067 |
np->estats.rx_runt + |
4068 |
np->estats.rx_frame_too_long + |
4069 |
np->rx_len_errors; |
4070 |
|
4071 |
/* copy to net_device stats */ |
4072 |
np->stats.tx_packets = np->estats.tx_packets; |
4073 |
np->stats.tx_fifo_errors = np->estats.tx_fifo_errors; |
4074 |
np->stats.tx_carrier_errors = np->estats.tx_carrier_errors; |
4075 |
np->stats.tx_bytes = np->estats.tx_bytes; |
4076 |
np->stats.rx_bytes = np->estats.rx_bytes; |
4077 |
np->stats.rx_crc_errors = np->estats.rx_crc_errors; |
4078 |
np->stats.rx_over_errors = np->estats.rx_over_errors; |
4079 |
np->stats.rx_packets = np->estats.rx_packets; |
4080 |
np->stats.rx_errors = np->estats.rx_errors_total; |
4081 |
|
4082 |
} else { |
4083 |
np->estats.tx_packets = np->stats.tx_packets; |
4084 |
np->estats.tx_fifo_errors = np->stats.tx_fifo_errors; |
4085 |
np->estats.tx_carrier_errors = np->stats.tx_carrier_errors; |
4086 |
np->estats.tx_bytes = np->stats.tx_bytes; |
4087 |
np->estats.rx_bytes = np->stats.rx_bytes; |
4088 |
np->estats.rx_crc_errors = np->stats.rx_crc_errors; |
4089 |
np->estats.rx_over_errors = np->stats.rx_over_errors; |
4090 |
np->estats.rx_packets = np->stats.rx_packets; |
4091 |
np->estats.rx_errors_total = np->stats.rx_errors; |
4092 |
} |
2861 |
|
4093 |
|
2862 |
if (!np->in_shutdown) |
4094 |
if (!np->in_shutdown && netif_running(dev)) |
2863 |
mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL); |
4095 |
mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL); |
|
|
4096 |
spin_unlock_irq(&np->lock); |
4097 |
} |
4098 |
|
4099 |
/* |
4100 |
* nv_get_stats: dev->get_stats function |
4101 |
* Get latest stats value from the nic. |
4102 |
* Called with read_lock(&dev_base_lock) held for read - |
4103 |
* only synchronized against unregister_netdevice. |
4104 |
*/ |
4105 |
static struct net_device_stats *nv_get_stats(struct net_device *dev) |
4106 |
{ |
4107 |
struct fe_priv *np = get_nvpriv(dev); |
4108 |
|
4109 |
/* It seems that the nic always generates interrupts and doesn't |
4110 |
* accumulate errors internally. Thus the current values in np->stats |
4111 |
* are already up to date. |
4112 |
*/ |
4113 |
nv_do_stats_poll((unsigned long)dev); |
4114 |
return &np->stats; |
2864 |
} |
4115 |
} |
2865 |
|
4116 |
|
2866 |
static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
4117 |
static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
2867 |
{ |
4118 |
{ |
2868 |
struct fe_priv *np = netdev_priv(dev); |
4119 |
struct fe_priv *np = get_nvpriv(dev); |
2869 |
strcpy(info->driver, "forcedeth"); |
4120 |
strcpy(info->driver, "forcedeth"); |
2870 |
strcpy(info->version, FORCEDETH_VERSION); |
4121 |
strcpy(info->version, FORCEDETH_VERSION); |
2871 |
strcpy(info->bus_info, pci_name(np->pci_dev)); |
4122 |
strcpy(info->bus_info, pci_name(np->pci_dev)); |
Lines 2873-2879
Link Here
|
2873 |
|
4124 |
|
2874 |
static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) |
4125 |
static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) |
2875 |
{ |
4126 |
{ |
2876 |
struct fe_priv *np = netdev_priv(dev); |
4127 |
struct fe_priv *np = get_nvpriv(dev); |
2877 |
wolinfo->supported = WAKE_MAGIC; |
4128 |
wolinfo->supported = WAKE_MAGIC; |
2878 |
|
4129 |
|
2879 |
spin_lock_irq(&np->lock); |
4130 |
spin_lock_irq(&np->lock); |
Lines 2884-2890
Link Here
|
2884 |
|
4135 |
|
2885 |
static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) |
4136 |
static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) |
2886 |
{ |
4137 |
{ |
2887 |
struct fe_priv *np = netdev_priv(dev); |
4138 |
struct fe_priv *np = get_nvpriv(dev); |
2888 |
u8 __iomem *base = get_hwbase(dev); |
4139 |
u8 __iomem *base = get_hwbase(dev); |
2889 |
u32 flags = 0; |
4140 |
u32 flags = 0; |
2890 |
|
4141 |
|
Lines 2904-2910
Link Here
|
2904 |
|
4155 |
|
2905 |
static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
4156 |
static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
2906 |
{ |
4157 |
{ |
2907 |
struct fe_priv *np = netdev_priv(dev); |
4158 |
struct fe_priv *np = get_nvpriv(dev); |
2908 |
int adv; |
4159 |
int adv; |
2909 |
|
4160 |
|
2910 |
spin_lock_irq(&np->lock); |
4161 |
spin_lock_irq(&np->lock); |
Lines 2978-2985
Link Here
|
2978 |
|
4229 |
|
2979 |
static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
4230 |
static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
2980 |
{ |
4231 |
{ |
2981 |
struct fe_priv *np = netdev_priv(dev); |
4232 |
struct fe_priv *np = get_nvpriv(dev); |
2982 |
|
4233 |
|
|
|
4234 |
dprintk(KERN_DEBUG "%s: nv_set_settings \n", dev->name); |
2983 |
if (ecmd->port != PORT_MII) |
4235 |
if (ecmd->port != PORT_MII) |
2984 |
return -EINVAL; |
4236 |
return -EINVAL; |
2985 |
if (ecmd->transceiver != XCVR_EXTERNAL) |
4237 |
if (ecmd->transceiver != XCVR_EXTERNAL) |
Lines 3057-3065
Link Here
|
3057 |
if (netif_running(dev)) |
4309 |
if (netif_running(dev)) |
3058 |
printk(KERN_INFO "%s: link down.\n", dev->name); |
4310 |
printk(KERN_INFO "%s: link down.\n", dev->name); |
3059 |
bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
4311 |
bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
|
|
4312 |
if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
4313 |
bmcr |= BMCR_ANENABLE; |
4314 |
/* reset the phy in order for settings to stick, |
4315 |
* and cause autoneg to start */ |
4316 |
if (phy_reset(dev, bmcr)) { |
4317 |
printk(KERN_INFO "%s: phy reset failed\n", dev->name); |
4318 |
return -EINVAL; |
4319 |
} |
4320 |
} else { |
3060 |
bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); |
4321 |
bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); |
3061 |
mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); |
4322 |
mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); |
3062 |
|
4323 |
} |
3063 |
} else { |
4324 |
} else { |
3064 |
int adv, bmcr; |
4325 |
int adv, bmcr; |
3065 |
|
4326 |
|
Lines 3099-3115
Link Here
|
3099 |
bmcr |= BMCR_FULLDPLX; |
4360 |
bmcr |= BMCR_FULLDPLX; |
3100 |
if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL)) |
4361 |
if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL)) |
3101 |
bmcr |= BMCR_SPEED100; |
4362 |
bmcr |= BMCR_SPEED100; |
3102 |
mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); |
|
|
3103 |
if (np->phy_oui == PHY_OUI_MARVELL) { |
4363 |
if (np->phy_oui == PHY_OUI_MARVELL) { |
3104 |
/* reset the phy */ |
4364 |
/* reset the phy in order for forced mode settings to stick */ |
3105 |
if (phy_reset(dev)) { |
4365 |
if (phy_reset(dev, bmcr)) { |
3106 |
printk(KERN_INFO "%s: phy reset failed\n", dev->name); |
4366 |
printk(KERN_INFO "%s: phy reset failed\n", dev->name); |
3107 |
return -EINVAL; |
4367 |
return -EINVAL; |
3108 |
} |
4368 |
} |
3109 |
} else if (netif_running(dev)) { |
4369 |
} else { |
3110 |
/* Wait a bit and then reconfigure the nic. */ |
4370 |
mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); |
3111 |
udelay(10); |
4371 |
if (netif_running(dev)) { |
3112 |
nv_linkchange(dev); |
4372 |
/* Wait a bit and then reconfigure the nic. */ |
|
|
4373 |
udelay(10); |
4374 |
nv_linkchange(dev); |
4375 |
} |
3113 |
} |
4376 |
} |
3114 |
} |
4377 |
} |
3115 |
|
4378 |
|
Lines 3126-3138
Link Here
|
3126 |
|
4389 |
|
3127 |
static int nv_get_regs_len(struct net_device *dev) |
4390 |
static int nv_get_regs_len(struct net_device *dev) |
3128 |
{ |
4391 |
{ |
3129 |
struct fe_priv *np = netdev_priv(dev); |
4392 |
struct fe_priv *np = get_nvpriv(dev); |
3130 |
return np->register_size; |
4393 |
return np->register_size; |
3131 |
} |
4394 |
} |
3132 |
|
4395 |
|
3133 |
static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) |
4396 |
static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) |
3134 |
{ |
4397 |
{ |
3135 |
struct fe_priv *np = netdev_priv(dev); |
4398 |
struct fe_priv *np = get_nvpriv(dev); |
3136 |
u8 __iomem *base = get_hwbase(dev); |
4399 |
u8 __iomem *base = get_hwbase(dev); |
3137 |
u32 *rbuf = buf; |
4400 |
u32 *rbuf = buf; |
3138 |
int i; |
4401 |
int i; |
Lines 3146-3152
Link Here
|
3146 |
|
4409 |
|
3147 |
static int nv_nway_reset(struct net_device *dev) |
4410 |
static int nv_nway_reset(struct net_device *dev) |
3148 |
{ |
4411 |
{ |
3149 |
struct fe_priv *np = netdev_priv(dev); |
4412 |
struct fe_priv *np = get_nvpriv(dev); |
3150 |
int ret; |
4413 |
int ret; |
3151 |
|
4414 |
|
3152 |
if (np->autoneg) { |
4415 |
if (np->autoneg) { |
Lines 3166-3173
Link Here
|
3166 |
} |
4429 |
} |
3167 |
|
4430 |
|
3168 |
bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
4431 |
bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
3169 |
bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); |
4432 |
if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
3170 |
mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); |
4433 |
bmcr |= BMCR_ANENABLE; |
|
|
4434 |
/* reset the phy in order for settings to stick*/ |
4435 |
if (phy_reset(dev, bmcr)) { |
4436 |
printk(KERN_INFO "%s: phy reset failed\n", dev->name); |
4437 |
return -EINVAL; |
4438 |
} |
4439 |
} else { |
4440 |
bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); |
4441 |
mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); |
4442 |
} |
3171 |
|
4443 |
|
3172 |
if (netif_running(dev)) { |
4444 |
if (netif_running(dev)) { |
3173 |
nv_start_rx(dev); |
4445 |
nv_start_rx(dev); |
Lines 3182-3200
Link Here
|
3182 |
return ret; |
4454 |
return ret; |
3183 |
} |
4455 |
} |
3184 |
|
4456 |
|
3185 |
static int nv_set_tso(struct net_device *dev, u32 value) |
|
|
3186 |
{ |
3187 |
struct fe_priv *np = netdev_priv(dev); |
3188 |
|
3189 |
if ((np->driver_data & DEV_HAS_CHECKSUM)) |
3190 |
return ethtool_op_set_tso(dev, value); |
3191 |
else |
3192 |
return -EOPNOTSUPP; |
3193 |
} |
3194 |
|
3195 |
static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) |
4457 |
static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) |
3196 |
{ |
4458 |
{ |
3197 |
struct fe_priv *np = netdev_priv(dev); |
4459 |
struct fe_priv *np = get_nvpriv(dev); |
3198 |
|
4460 |
|
3199 |
ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; |
4461 |
ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; |
3200 |
ring->rx_mini_max_pending = 0; |
4462 |
ring->rx_mini_max_pending = 0; |
Lines 3209-3228
Link Here
|
3209 |
|
4471 |
|
3210 |
static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) |
4472 |
static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) |
3211 |
{ |
4473 |
{ |
3212 |
struct fe_priv *np = netdev_priv(dev); |
4474 |
struct fe_priv *np = get_nvpriv(dev); |
3213 |
u8 __iomem *base = get_hwbase(dev); |
4475 |
u8 __iomem *base = get_hwbase(dev); |
3214 |
u8 *rxtx_ring, *rx_skbuff, *tx_skbuff, *rx_dma, *tx_dma, *tx_dma_len; |
4476 |
u8 *rxtx_ring, *rx_skbuff, *tx_skbuff; |
3215 |
dma_addr_t ring_addr; |
4477 |
dma_addr_t ring_addr; |
3216 |
|
4478 |
|
3217 |
if (ring->rx_pending < RX_RING_MIN || |
4479 |
if (ring->rx_pending < RX_RING_MIN || |
3218 |
ring->tx_pending < TX_RING_MIN || |
4480 |
ring->tx_pending < TX_RING_MIN || |
3219 |
ring->rx_mini_pending != 0 || |
4481 |
ring->rx_mini_pending != 0 || |
3220 |
ring->rx_jumbo_pending != 0 || |
4482 |
ring->rx_jumbo_pending != 0 || |
3221 |
(np->desc_ver == DESC_VER_1 && |
4483 |
(np->desc_ver == DESC_VER_1 && |
3222 |
(ring->rx_pending > RING_MAX_DESC_VER_1 || |
4484 |
(ring->rx_pending > RING_MAX_DESC_VER_1 || |
3223 |
ring->tx_pending > RING_MAX_DESC_VER_1)) || |
4485 |
ring->tx_pending > RING_MAX_DESC_VER_1)) || |
3224 |
(np->desc_ver != DESC_VER_1 && |
4486 |
(np->desc_ver != DESC_VER_1 && |
3225 |
(ring->rx_pending > RING_MAX_DESC_VER_2_3 || |
4487 |
(ring->rx_pending > RING_MAX_DESC_VER_2_3 || |
3226 |
ring->tx_pending > RING_MAX_DESC_VER_2_3))) { |
4488 |
ring->tx_pending > RING_MAX_DESC_VER_2_3))) { |
3227 |
return -EINVAL; |
4489 |
return -EINVAL; |
3228 |
} |
4490 |
} |
Lines 3237-3248
Link Here
|
3237 |
sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending), |
4499 |
sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending), |
3238 |
&ring_addr); |
4500 |
&ring_addr); |
3239 |
} |
4501 |
} |
3240 |
rx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->rx_pending, GFP_KERNEL); |
4502 |
rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL); |
3241 |
rx_dma = kmalloc(sizeof(dma_addr_t) * ring->rx_pending, GFP_KERNEL); |
4503 |
tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL); |
3242 |
tx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->tx_pending, GFP_KERNEL); |
4504 |
|
3243 |
tx_dma = kmalloc(sizeof(dma_addr_t) * ring->tx_pending, GFP_KERNEL); |
4505 |
if (!rxtx_ring || !rx_skbuff || !tx_skbuff) { |
3244 |
tx_dma_len = kmalloc(sizeof(unsigned int) * ring->tx_pending, GFP_KERNEL); |
|
|
3245 |
if (!rxtx_ring || !rx_skbuff || !rx_dma || !tx_skbuff || !tx_dma || !tx_dma_len) { |
3246 |
/* fall back to old rings */ |
4506 |
/* fall back to old rings */ |
3247 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
4507 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
3248 |
if(rxtx_ring) |
4508 |
if(rxtx_ring) |
Lines 3255-3268
Link Here
|
3255 |
} |
4515 |
} |
3256 |
if (rx_skbuff) |
4516 |
if (rx_skbuff) |
3257 |
kfree(rx_skbuff); |
4517 |
kfree(rx_skbuff); |
3258 |
if (rx_dma) |
|
|
3259 |
kfree(rx_dma); |
3260 |
if (tx_skbuff) |
4518 |
if (tx_skbuff) |
3261 |
kfree(tx_skbuff); |
4519 |
kfree(tx_skbuff); |
3262 |
if (tx_dma) |
|
|
3263 |
kfree(tx_dma); |
3264 |
if (tx_dma_len) |
3265 |
kfree(tx_dma_len); |
3266 |
goto exit; |
4520 |
goto exit; |
3267 |
} |
4521 |
} |
3268 |
|
4522 |
|
Lines 3280-3291
Link Here
|
3280 |
/* delete queues */ |
4534 |
/* delete queues */ |
3281 |
free_rings(dev); |
4535 |
free_rings(dev); |
3282 |
} |
4536 |
} |
3283 |
|
4537 |
|
3284 |
/* set new values */ |
4538 |
/* set new values */ |
3285 |
np->rx_ring_size = ring->rx_pending; |
4539 |
np->rx_ring_size = ring->rx_pending; |
3286 |
np->tx_ring_size = ring->tx_pending; |
4540 |
np->tx_ring_size = ring->tx_pending; |
3287 |
np->tx_limit_stop = ring->tx_pending - TX_LIMIT_DIFFERENCE; |
4541 |
np->tx_limit_stop =np->tx_ring_size - TX_LIMIT_DIFFERENCE; |
3288 |
np->tx_limit_start = ring->tx_pending - TX_LIMIT_DIFFERENCE - 1; |
4542 |
np->tx_limit_start =np->tx_ring_size - TX_LIMIT_DIFFERENCE - 1; |
3289 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
4543 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
3290 |
np->rx_ring.orig = (struct ring_desc*)rxtx_ring; |
4544 |
np->rx_ring.orig = (struct ring_desc*)rxtx_ring; |
3291 |
np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; |
4545 |
np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; |
Lines 3293-3310
Link Here
|
3293 |
np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring; |
4547 |
np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring; |
3294 |
np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; |
4548 |
np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; |
3295 |
} |
4549 |
} |
3296 |
np->rx_skbuff = (struct sk_buff**)rx_skbuff; |
4550 |
np->rx_skb = (struct nv_skb_map*)rx_skbuff; |
3297 |
np->rx_dma = (dma_addr_t*)rx_dma; |
4551 |
np->tx_skb = (struct nv_skb_map*)tx_skbuff; |
3298 |
np->tx_skbuff = (struct sk_buff**)tx_skbuff; |
|
|
3299 |
np->tx_dma = (dma_addr_t*)tx_dma; |
3300 |
np->tx_dma_len = (unsigned int*)tx_dma_len; |
3301 |
np->ring_addr = ring_addr; |
4552 |
np->ring_addr = ring_addr; |
3302 |
|
4553 |
|
3303 |
memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size); |
4554 |
memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size); |
3304 |
memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size); |
4555 |
memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size); |
3305 |
memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size); |
|
|
3306 |
memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size); |
3307 |
memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size); |
3308 |
|
4556 |
|
3309 |
if (netif_running(dev)) { |
4557 |
if (netif_running(dev)) { |
3310 |
/* reinit driver view of the queues */ |
4558 |
/* reinit driver view of the queues */ |
Lines 3313-3319
Link Here
|
3313 |
if (!np->in_shutdown) |
4561 |
if (!np->in_shutdown) |
3314 |
mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
4562 |
mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
3315 |
} |
4563 |
} |
3316 |
|
4564 |
|
3317 |
/* reinit nic view of the queues */ |
4565 |
/* reinit nic view of the queues */ |
3318 |
writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
4566 |
writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
3319 |
setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
4567 |
setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
Lines 3322-3328
Link Here
|
3322 |
pci_push(base); |
4570 |
pci_push(base); |
3323 |
writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
4571 |
writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
3324 |
pci_push(base); |
4572 |
pci_push(base); |
3325 |
|
4573 |
|
3326 |
/* restart engines */ |
4574 |
/* restart engines */ |
3327 |
nv_start_rx(dev); |
4575 |
nv_start_rx(dev); |
3328 |
nv_start_tx(dev); |
4576 |
nv_start_tx(dev); |
Lines 3337-3343
Link Here
|
3337 |
|
4585 |
|
3338 |
static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause) |
4586 |
static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause) |
3339 |
{ |
4587 |
{ |
3340 |
struct fe_priv *np = netdev_priv(dev); |
4588 |
struct fe_priv *np = get_nvpriv(dev); |
3341 |
|
4589 |
|
3342 |
pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0; |
4590 |
pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0; |
3343 |
pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0; |
4591 |
pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0; |
Lines 3346-3357
Link Here
|
3346 |
|
4594 |
|
3347 |
static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause) |
4595 |
static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause) |
3348 |
{ |
4596 |
{ |
3349 |
struct fe_priv *np = netdev_priv(dev); |
4597 |
struct fe_priv *np = get_nvpriv(dev); |
3350 |
int adv, bmcr; |
4598 |
int adv, bmcr; |
3351 |
|
4599 |
|
3352 |
if ((!np->autoneg && np->duplex == 0) || |
4600 |
if ((!np->autoneg && np->duplex == 0) || |
3353 |
(np->autoneg && !pause->autoneg && np->duplex == 0)) { |
4601 |
(np->autoneg && !pause->autoneg && np->duplex == 0)) { |
3354 |
printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n", |
4602 |
printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n", |
3355 |
dev->name); |
4603 |
dev->name); |
3356 |
return -EINVAL; |
4604 |
return -EINVAL; |
3357 |
} |
4605 |
} |
Lines 3417-3447
Link Here
|
3417 |
|
4665 |
|
3418 |
static u32 nv_get_rx_csum(struct net_device *dev) |
4666 |
static u32 nv_get_rx_csum(struct net_device *dev) |
3419 |
{ |
4667 |
{ |
3420 |
struct fe_priv *np = netdev_priv(dev); |
4668 |
struct fe_priv *np = get_nvpriv(dev); |
3421 |
return (np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) != 0; |
4669 |
return (np->rx_csum) != 0; |
3422 |
} |
4670 |
} |
3423 |
|
4671 |
|
3424 |
static int nv_set_rx_csum(struct net_device *dev, u32 data) |
4672 |
static int nv_set_rx_csum(struct net_device *dev, u32 data) |
3425 |
{ |
4673 |
{ |
3426 |
struct fe_priv *np = netdev_priv(dev); |
4674 |
struct fe_priv *np = get_nvpriv(dev); |
3427 |
u8 __iomem *base = get_hwbase(dev); |
4675 |
u8 __iomem *base = get_hwbase(dev); |
3428 |
int retcode = 0; |
4676 |
int retcode = 0; |
3429 |
|
4677 |
|
3430 |
if (np->driver_data & DEV_HAS_CHECKSUM) { |
4678 |
if (np->driver_data & DEV_HAS_CHECKSUM) { |
3431 |
|
4679 |
|
3432 |
if (((np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) && data) || |
|
|
3433 |
(!(np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) && !data)) { |
3434 |
/* already set or unset */ |
3435 |
return 0; |
3436 |
} |
3437 |
|
3438 |
if (data) { |
4680 |
if (data) { |
|
|
4681 |
np->rx_csum = 1; |
3439 |
np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; |
4682 |
np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; |
3440 |
} else if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE)) { |
|
|
3441 |
np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK; |
3442 |
} else { |
4683 |
} else { |
3443 |
printk(KERN_INFO "Can not disable rx checksum if vlan is enabled\n"); |
4684 |
np->rx_csum = 0; |
3444 |
return -EINVAL; |
4685 |
/* vlan is dependent on rx checksum offload */ |
|
|
4686 |
if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE)) |
4687 |
np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK; |
3445 |
} |
4688 |
} |
3446 |
|
4689 |
|
3447 |
if (netif_running(dev)) { |
4690 |
if (netif_running(dev)) { |
Lines 3456-3494
Link Here
|
3456 |
return retcode; |
4699 |
return retcode; |
3457 |
} |
4700 |
} |
3458 |
|
4701 |
|
3459 |
static int nv_set_tx_csum(struct net_device *dev, u32 data) |
4702 |
#ifdef NETIF_F_TSO |
|
|
4703 |
static int nv_set_tso(struct net_device *dev, u32 data) |
3460 |
{ |
4704 |
{ |
3461 |
struct fe_priv *np = netdev_priv(dev); |
4705 |
struct fe_priv *np = get_nvpriv(dev); |
3462 |
|
4706 |
|
3463 |
if (np->driver_data & DEV_HAS_CHECKSUM) |
4707 |
if (np->driver_data & DEV_HAS_CHECKSUM){ |
3464 |
return ethtool_op_set_tx_hw_csum(dev, data); |
4708 |
#if NVVER < SUSE10 |
3465 |
else |
4709 |
if(data){ |
3466 |
return -EOPNOTSUPP; |
4710 |
if(ethtool_op_get_sg(dev)==0) |
|
|
4711 |
return -EINVAL; |
4712 |
} |
4713 |
#endif |
4714 |
return ethtool_op_set_tso(dev, data); |
4715 |
}else |
4716 |
return -EINVAL; |
3467 |
} |
4717 |
} |
|
|
4718 |
#endif |
3468 |
|
4719 |
|
3469 |
static int nv_set_sg(struct net_device *dev, u32 data) |
4720 |
static int nv_set_sg(struct net_device *dev, u32 data) |
3470 |
{ |
4721 |
{ |
3471 |
struct fe_priv *np = netdev_priv(dev); |
4722 |
struct fe_priv *np = get_nvpriv(dev); |
|
|
4723 |
|
4724 |
if (np->driver_data & DEV_HAS_CHECKSUM){ |
4725 |
#if NVVER < SUSE10 |
4726 |
if(data){ |
4727 |
if(ethtool_op_get_tx_csum(dev)==0) |
4728 |
return -EINVAL; |
4729 |
} |
4730 |
#ifdef NETIF_F_TSO |
4731 |
if(!data) |
4732 |
/* set tso off */ |
4733 |
nv_set_tso(dev,data); |
4734 |
#endif |
4735 |
#endif |
4736 |
return ethtool_op_set_sg(dev, data); |
4737 |
}else |
4738 |
return -EINVAL; |
4739 |
} |
3472 |
|
4740 |
|
|
|
4741 |
static int nv_set_tx_csum(struct net_device *dev, u32 data) |
4742 |
{ |
4743 |
struct fe_priv *np = get_nvpriv(dev); |
4744 |
|
4745 |
#if NVVER < SUSE10 |
4746 |
/* set sg off if tx off */ |
4747 |
if(!data) |
4748 |
nv_set_sg(dev,data); |
4749 |
#endif |
3473 |
if (np->driver_data & DEV_HAS_CHECKSUM) |
4750 |
if (np->driver_data & DEV_HAS_CHECKSUM) |
3474 |
return ethtool_op_set_sg(dev, data); |
4751 |
#if NVVER > RHES4 |
|
|
4752 |
return ethtool_op_set_tx_hw_csum(dev, data); |
4753 |
#else |
4754 |
{ |
4755 |
if (data) |
4756 |
dev->features |= NETIF_F_IP_CSUM; |
4757 |
else |
4758 |
dev->features &= ~NETIF_F_IP_CSUM; |
4759 |
return 0; |
4760 |
} |
4761 |
#endif |
3475 |
else |
4762 |
else |
3476 |
return -EOPNOTSUPP; |
4763 |
return -EINVAL; |
3477 |
} |
4764 |
} |
3478 |
|
4765 |
|
3479 |
static int nv_get_stats_count(struct net_device *dev) |
4766 |
static int nv_get_stats_count(struct net_device *dev) |
3480 |
{ |
4767 |
{ |
3481 |
struct fe_priv *np = netdev_priv(dev); |
4768 |
struct fe_priv *np = get_nvpriv(dev); |
3482 |
|
4769 |
|
3483 |
if (np->driver_data & DEV_HAS_STATISTICS) |
4770 |
if (np->driver_data & DEV_HAS_STATISTICS) |
3484 |
return (sizeof(struct nv_ethtool_stats)/sizeof(u64)); |
4771 |
return (sizeof(struct nv_ethtool_stats)/sizeof(u64)); |
3485 |
else |
4772 |
else |
3486 |
return 0; |
4773 |
return NV_STATS_COUNT_SW; |
3487 |
} |
4774 |
} |
3488 |
|
4775 |
|
3489 |
static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer) |
4776 |
static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer) |
3490 |
{ |
4777 |
{ |
3491 |
struct fe_priv *np = netdev_priv(dev); |
4778 |
struct fe_priv *np = get_nvpriv(dev); |
3492 |
|
4779 |
|
3493 |
/* update stats */ |
4780 |
/* update stats */ |
3494 |
nv_do_stats_poll((unsigned long)dev); |
4781 |
nv_do_stats_poll((unsigned long)dev); |
Lines 3498-3504
Link Here
|
3498 |
|
4785 |
|
3499 |
static int nv_self_test_count(struct net_device *dev) |
4786 |
static int nv_self_test_count(struct net_device *dev) |
3500 |
{ |
4787 |
{ |
3501 |
struct fe_priv *np = netdev_priv(dev); |
4788 |
struct fe_priv *np = get_nvpriv(dev); |
3502 |
|
4789 |
|
3503 |
if (np->driver_data & DEV_HAS_TEST_EXTENDED) |
4790 |
if (np->driver_data & DEV_HAS_TEST_EXTENDED) |
3504 |
return NV_TEST_COUNT_EXTENDED; |
4791 |
return NV_TEST_COUNT_EXTENDED; |
Lines 3508-3514
Link Here
|
3508 |
|
4795 |
|
3509 |
static int nv_link_test(struct net_device *dev) |
4796 |
static int nv_link_test(struct net_device *dev) |
3510 |
{ |
4797 |
{ |
3511 |
struct fe_priv *np = netdev_priv(dev); |
4798 |
struct fe_priv *np = get_nvpriv(dev); |
3512 |
int mii_status; |
4799 |
int mii_status; |
3513 |
|
4800 |
|
3514 |
mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); |
4801 |
mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); |
Lines 3551-3557
Link Here
|
3551 |
|
4838 |
|
3552 |
static int nv_interrupt_test(struct net_device *dev) |
4839 |
static int nv_interrupt_test(struct net_device *dev) |
3553 |
{ |
4840 |
{ |
3554 |
struct fe_priv *np = netdev_priv(dev); |
4841 |
struct fe_priv *np = get_nvpriv(dev); |
3555 |
u8 __iomem *base = get_hwbase(dev); |
4842 |
u8 __iomem *base = get_hwbase(dev); |
3556 |
int ret = 1; |
4843 |
int ret = 1; |
3557 |
int testcnt; |
4844 |
int testcnt; |
Lines 3580-3586
Link Here
|
3580 |
nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER); |
4867 |
nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER); |
3581 |
|
4868 |
|
3582 |
/* wait for at least one interrupt */ |
4869 |
/* wait for at least one interrupt */ |
3583 |
msleep(100); |
4870 |
nv_msleep(100); |
3584 |
|
4871 |
|
3585 |
spin_lock_irq(&np->lock); |
4872 |
spin_lock_irq(&np->lock); |
3586 |
|
4873 |
|
Lines 3614-3620
Link Here
|
3614 |
|
4901 |
|
3615 |
static int nv_loopback_test(struct net_device *dev) |
4902 |
static int nv_loopback_test(struct net_device *dev) |
3616 |
{ |
4903 |
{ |
3617 |
struct fe_priv *np = netdev_priv(dev); |
4904 |
struct fe_priv *np = get_nvpriv(dev); |
3618 |
u8 __iomem *base = get_hwbase(dev); |
4905 |
u8 __iomem *base = get_hwbase(dev); |
3619 |
struct sk_buff *tx_skb, *rx_skb; |
4906 |
struct sk_buff *tx_skb, *rx_skb; |
3620 |
dma_addr_t test_dma_addr; |
4907 |
dma_addr_t test_dma_addr; |
Lines 3673-3685
Link Here
|
3673 |
writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
4960 |
writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
3674 |
pci_push(get_hwbase(dev)); |
4961 |
pci_push(get_hwbase(dev)); |
3675 |
|
4962 |
|
3676 |
msleep(500); |
4963 |
nv_msleep(500); |
3677 |
|
4964 |
|
3678 |
/* check for rx of the packet */ |
4965 |
/* check for rx of the packet */ |
3679 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
4966 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
3680 |
Flags = le32_to_cpu(np->rx_ring.orig[0].FlagLen); |
4967 |
Flags = le32_to_cpu(np->rx_ring.orig[0].FlagLen); |
3681 |
len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver); |
4968 |
len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver); |
3682 |
|
4969 |
|
3683 |
} else { |
4970 |
} else { |
3684 |
Flags = le32_to_cpu(np->rx_ring.ex[0].FlagLen); |
4971 |
Flags = le32_to_cpu(np->rx_ring.ex[0].FlagLen); |
3685 |
len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver); |
4972 |
len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver); |
Lines 3696-3712
Link Here
|
3696 |
} |
4983 |
} |
3697 |
} |
4984 |
} |
3698 |
|
4985 |
|
3699 |
if (ret) { |
4986 |
if (ret) { |
3700 |
if (len != pkt_len) { |
4987 |
if (len != pkt_len) { |
3701 |
ret = 0; |
4988 |
ret = 0; |
3702 |
dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n", |
4989 |
dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n", |
3703 |
dev->name, len, pkt_len); |
4990 |
dev->name, len, pkt_len); |
3704 |
} else { |
4991 |
} else { |
3705 |
rx_skb = np->rx_skbuff[0]; |
4992 |
rx_skb = np->rx_skb[0].skb; |
3706 |
for (i = 0; i < pkt_len; i++) { |
4993 |
for (i = 0; i < pkt_len; i++) { |
3707 |
if (rx_skb->data[i] != (u8)(i & 0xff)) { |
4994 |
if (rx_skb->data[i] != (u8)(i & 0xff)) { |
3708 |
ret = 0; |
4995 |
ret = 0; |
3709 |
dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n", |
4996 |
dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n", |
3710 |
dev->name, i); |
4997 |
dev->name, i); |
3711 |
break; |
4998 |
break; |
3712 |
} |
4999 |
} |
Lines 3720-3726
Link Here
|
3720 |
tx_skb->end-tx_skb->data, |
5007 |
tx_skb->end-tx_skb->data, |
3721 |
PCI_DMA_TODEVICE); |
5008 |
PCI_DMA_TODEVICE); |
3722 |
dev_kfree_skb_any(tx_skb); |
5009 |
dev_kfree_skb_any(tx_skb); |
3723 |
|
5010 |
|
3724 |
/* stop engines */ |
5011 |
/* stop engines */ |
3725 |
nv_stop_rx(dev); |
5012 |
nv_stop_rx(dev); |
3726 |
nv_stop_tx(dev); |
5013 |
nv_stop_tx(dev); |
Lines 3740-3746
Link Here
|
3740 |
|
5027 |
|
3741 |
static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer) |
5028 |
static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer) |
3742 |
{ |
5029 |
{ |
3743 |
struct fe_priv *np = netdev_priv(dev); |
5030 |
struct fe_priv *np = get_nvpriv(dev); |
3744 |
u8 __iomem *base = get_hwbase(dev); |
5031 |
u8 __iomem *base = get_hwbase(dev); |
3745 |
int result; |
5032 |
int result; |
3746 |
memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64)); |
5033 |
memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64)); |
Lines 3838-3846
Link Here
|
3838 |
.get_regs_len = nv_get_regs_len, |
5125 |
.get_regs_len = nv_get_regs_len, |
3839 |
.get_regs = nv_get_regs, |
5126 |
.get_regs = nv_get_regs, |
3840 |
.nway_reset = nv_nway_reset, |
5127 |
.nway_reset = nv_nway_reset, |
|
|
5128 |
#if NVVER > SUSE10 |
3841 |
.get_perm_addr = ethtool_op_get_perm_addr, |
5129 |
.get_perm_addr = ethtool_op_get_perm_addr, |
3842 |
.get_tso = ethtool_op_get_tso, |
5130 |
#endif |
3843 |
.set_tso = nv_set_tso, |
|
|
3844 |
.get_ringparam = nv_get_ringparam, |
5131 |
.get_ringparam = nv_get_ringparam, |
3845 |
.set_ringparam = nv_set_ringparam, |
5132 |
.set_ringparam = nv_set_ringparam, |
3846 |
.get_pauseparam = nv_get_pauseparam, |
5133 |
.get_pauseparam = nv_get_pauseparam, |
Lines 3851-3856
Link Here
|
3851 |
.set_tx_csum = nv_set_tx_csum, |
5138 |
.set_tx_csum = nv_set_tx_csum, |
3852 |
.get_sg = ethtool_op_get_sg, |
5139 |
.get_sg = ethtool_op_get_sg, |
3853 |
.set_sg = nv_set_sg, |
5140 |
.set_sg = nv_set_sg, |
|
|
5141 |
#ifdef NETIF_F_TSO |
5142 |
.get_tso = ethtool_op_get_tso, |
5143 |
.set_tso = nv_set_tso, |
5144 |
#endif |
3854 |
.get_strings = nv_get_strings, |
5145 |
.get_strings = nv_get_strings, |
3855 |
.get_stats_count = nv_get_stats_count, |
5146 |
.get_stats_count = nv_get_stats_count, |
3856 |
.get_ethtool_stats = nv_get_ethtool_stats, |
5147 |
.get_ethtool_stats = nv_get_ethtool_stats, |
Lines 3870-3879
Link Here
|
3870 |
if (grp) { |
5161 |
if (grp) { |
3871 |
/* enable vlan on MAC */ |
5162 |
/* enable vlan on MAC */ |
3872 |
np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS; |
5163 |
np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS; |
|
|
5164 |
np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; |
3873 |
} else { |
5165 |
} else { |
3874 |
/* disable vlan on MAC */ |
5166 |
/* disable vlan on MAC */ |
3875 |
np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP; |
5167 |
np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP; |
3876 |
np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS; |
5168 |
np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS; |
|
|
5169 |
if (!np->rx_csum) |
5170 |
np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK; |
3877 |
} |
5171 |
} |
3878 |
|
5172 |
|
3879 |
writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
5173 |
writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
Lines 3886-3938
Link Here
|
3886 |
/* nothing to do */ |
5180 |
/* nothing to do */ |
3887 |
}; |
5181 |
}; |
3888 |
|
5182 |
|
|
|
5183 |
/* The mgmt unit and driver use a semaphore to access the phy during init */ |
5184 |
static int nv_mgmt_acquire_sema(struct net_device *dev) |
5185 |
{ |
5186 |
u8 __iomem *base = get_hwbase(dev); |
5187 |
int i; |
5188 |
u32 tx_ctrl, mgmt_sema; |
5189 |
|
5190 |
for (i = 0; i < 10; i++) { |
5191 |
mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK; |
5192 |
if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE) { |
5193 |
dprintk(KERN_INFO "forcedeth: nv_mgmt_acquire_sema: sema is free\n"); |
5194 |
break; |
5195 |
} |
5196 |
nv_msleep(500); |
5197 |
} |
5198 |
|
5199 |
if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE) { |
5200 |
dprintk(KERN_INFO "forcedeth: nv_mgmt_acquire_sema: sema is not free\n"); |
5201 |
return 0; |
5202 |
} |
5203 |
|
5204 |
for (i = 0; i < 2; i++) { |
5205 |
tx_ctrl = readl(base + NvRegTransmitterControl); |
5206 |
tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ; |
5207 |
writel(tx_ctrl, base + NvRegTransmitterControl); |
5208 |
|
5209 |
/* verify that semaphore was acquired */ |
5210 |
tx_ctrl = readl(base + NvRegTransmitterControl); |
5211 |
if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) && |
5212 |
((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) { |
5213 |
dprintk(KERN_INFO "forcedeth: nv_mgmt_acquire_sema: acquired sema\n"); |
5214 |
return 1; |
5215 |
} else |
5216 |
udelay(50); |
5217 |
} |
5218 |
|
5219 |
dprintk(KERN_INFO "forcedeth: nv_mgmt_acquire_sema: exit\n"); |
5220 |
return 0; |
5221 |
} |
5222 |
|
5223 |
/* Indicate to mgmt unit whether driver is loaded or not */ |
5224 |
static void nv_mgmt_driver_loaded(struct net_device *dev, int loaded) |
5225 |
{ |
5226 |
u8 __iomem *base = get_hwbase(dev); |
5227 |
u32 tx_ctrl; |
5228 |
|
5229 |
tx_ctrl = readl(base + NvRegTransmitterControl); |
5230 |
if (loaded) |
5231 |
tx_ctrl |= NVREG_XMITCTL_HOST_LOADED; |
5232 |
else |
5233 |
tx_ctrl &= ~NVREG_XMITCTL_HOST_LOADED; |
5234 |
writel(tx_ctrl, base + NvRegTransmitterControl); |
5235 |
} |
5236 |
|
3889 |
static int nv_open(struct net_device *dev) |
5237 |
static int nv_open(struct net_device *dev) |
3890 |
{ |
5238 |
{ |
3891 |
struct fe_priv *np = netdev_priv(dev); |
5239 |
struct fe_priv *np = get_nvpriv(dev); |
3892 |
u8 __iomem *base = get_hwbase(dev); |
5240 |
u8 __iomem *base = get_hwbase(dev); |
3893 |
int ret = 1; |
5241 |
int ret = 1; |
3894 |
int oom, i; |
5242 |
int oom, i; |
3895 |
|
5243 |
|
3896 |
dprintk(KERN_DEBUG "nv_open: begin\n"); |
5244 |
dprintk(KERN_DEBUG "nv_open: begin\n"); |
3897 |
|
5245 |
|
3898 |
/* 1) erase previous misconfiguration */ |
5246 |
/* erase previous misconfiguration */ |
3899 |
if (np->driver_data & DEV_HAS_POWER_CNTRL) |
5247 |
if (np->driver_data & DEV_HAS_POWER_CNTRL) |
3900 |
nv_mac_reset(dev); |
5248 |
nv_mac_reset(dev); |
3901 |
/* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */ |
5249 |
/* stop adapter: ignored, 4.3 seems to be overkill */ |
3902 |
writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); |
5250 |
writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); |
3903 |
writel(0, base + NvRegMulticastAddrB); |
5251 |
writel(0, base + NvRegMulticastAddrB); |
3904 |
writel(0, base + NvRegMulticastMaskA); |
5252 |
writel(0, base + NvRegMulticastMaskA); |
3905 |
writel(0, base + NvRegMulticastMaskB); |
5253 |
writel(0, base + NvRegMulticastMaskB); |
3906 |
writel(0, base + NvRegPacketFilterFlags); |
5254 |
writel(0, base + NvRegPacketFilterFlags); |
3907 |
|
5255 |
|
3908 |
writel(0, base + NvRegTransmitterControl); |
5256 |
nv_stop_tx(dev); |
3909 |
writel(0, base + NvRegReceiverControl); |
5257 |
nv_stop_rx(dev); |
3910 |
|
5258 |
|
3911 |
writel(0, base + NvRegAdapterControl); |
5259 |
writel(0, base + NvRegAdapterControl); |
3912 |
|
5260 |
|
3913 |
if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) |
5261 |
if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) |
3914 |
writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); |
5262 |
writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); |
3915 |
|
5263 |
|
3916 |
/* 2) initialize descriptor rings */ |
5264 |
/* initialize descriptor rings */ |
3917 |
set_bufsize(dev); |
5265 |
set_bufsize(dev); |
3918 |
oom = nv_init_ring(dev); |
5266 |
oom = nv_init_ring(dev); |
3919 |
|
5267 |
|
3920 |
writel(0, base + NvRegLinkSpeed); |
|
|
3921 |
writel(0, base + NvRegUnknownTransmitterReg); |
3922 |
nv_txrx_reset(dev); |
5268 |
nv_txrx_reset(dev); |
3923 |
writel(0, base + NvRegUnknownSetupReg6); |
5269 |
writel(0, base + NvRegUnknownSetupReg6); |
3924 |
|
5270 |
|
3925 |
np->in_shutdown = 0; |
5271 |
np->in_shutdown = 0; |
3926 |
|
5272 |
|
3927 |
/* 3) set mac address */ |
5273 |
/* give hw rings */ |
3928 |
nv_copy_mac_to_hw(dev); |
|
|
3929 |
|
3930 |
/* 4) give hw rings */ |
3931 |
setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
5274 |
setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
3932 |
writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
5275 |
writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
3933 |
base + NvRegRingSizes); |
5276 |
base + NvRegRingSizes); |
3934 |
|
5277 |
|
3935 |
/* 5) continue setup */ |
5278 |
/* continue setup */ |
3936 |
writel(np->linkspeed, base + NvRegLinkSpeed); |
5279 |
writel(np->linkspeed, base + NvRegLinkSpeed); |
3937 |
if (np->desc_ver == DESC_VER_1) |
5280 |
if (np->desc_ver == DESC_VER_1) |
3938 |
writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark); |
5281 |
writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark); |
Lines 3946-3956
Link Here
|
3946 |
NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX, |
5289 |
NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX, |
3947 |
KERN_INFO "open: SetupReg5, Bit 31 remained off\n"); |
5290 |
KERN_INFO "open: SetupReg5, Bit 31 remained off\n"); |
3948 |
|
5291 |
|
3949 |
writel(0, base + NvRegUnknownSetupReg4); |
5292 |
writel(0, base + NvRegMIIMask); |
3950 |
writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
5293 |
writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
3951 |
writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus); |
5294 |
writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus); |
3952 |
|
5295 |
|
3953 |
/* 6) continue setup */ |
5296 |
/* continue setup */ |
3954 |
writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1); |
5297 |
writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1); |
3955 |
writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus); |
5298 |
writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus); |
3956 |
writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags); |
5299 |
writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags); |
Lines 3973-3979
Link Here
|
3973 |
writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, |
5316 |
writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, |
3974 |
base + NvRegAdapterControl); |
5317 |
base + NvRegAdapterControl); |
3975 |
writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed); |
5318 |
writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed); |
3976 |
writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4); |
5319 |
writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask); |
3977 |
if (np->wolenabled) |
5320 |
if (np->wolenabled) |
3978 |
writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags); |
5321 |
writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags); |
3979 |
|
5322 |
|
Lines 4023-4037
Link Here
|
4023 |
if (ret) { |
5366 |
if (ret) { |
4024 |
netif_carrier_on(dev); |
5367 |
netif_carrier_on(dev); |
4025 |
} else { |
5368 |
} else { |
4026 |
printk("%s: no link during initialization.\n", dev->name); |
5369 |
dprintk(KERN_DEBUG "%s: no link during initialization.\n", dev->name); |
4027 |
netif_carrier_off(dev); |
5370 |
netif_carrier_off(dev); |
4028 |
} |
5371 |
} |
4029 |
if (oom) |
5372 |
if (oom) |
4030 |
mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
5373 |
mod_timer(&np->oom_kick, jiffies + OOM_REFILL); |
4031 |
|
5374 |
|
4032 |
/* start statistics timer */ |
5375 |
/* start statistics timer */ |
4033 |
if (np->driver_data & DEV_HAS_STATISTICS) |
5376 |
mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL); |
4034 |
mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL); |
|
|
4035 |
|
5377 |
|
4036 |
spin_unlock_irq(&np->lock); |
5378 |
spin_unlock_irq(&np->lock); |
4037 |
|
5379 |
|
Lines 4043-4055
Link Here
|
4043 |
|
5385 |
|
4044 |
static int nv_close(struct net_device *dev) |
5386 |
static int nv_close(struct net_device *dev) |
4045 |
{ |
5387 |
{ |
4046 |
struct fe_priv *np = netdev_priv(dev); |
5388 |
struct fe_priv *np = get_nvpriv(dev); |
4047 |
u8 __iomem *base; |
5389 |
u8 __iomem *base; |
4048 |
|
5390 |
|
|
|
5391 |
dprintk(KERN_DEBUG "nv_close: begin\n"); |
4049 |
spin_lock_irq(&np->lock); |
5392 |
spin_lock_irq(&np->lock); |
4050 |
np->in_shutdown = 1; |
5393 |
np->in_shutdown = 1; |
4051 |
spin_unlock_irq(&np->lock); |
5394 |
spin_unlock_irq(&np->lock); |
|
|
5395 |
|
5396 |
#if NVVER > RHES3 |
4052 |
synchronize_irq(dev->irq); |
5397 |
synchronize_irq(dev->irq); |
|
|
5398 |
#else |
5399 |
synchronize_irq(); |
5400 |
#endif |
4053 |
|
5401 |
|
4054 |
del_timer_sync(&np->oom_kick); |
5402 |
del_timer_sync(&np->oom_kick); |
4055 |
del_timer_sync(&np->nic_poll); |
5403 |
del_timer_sync(&np->nic_poll); |
Lines 4076-4087
Link Here
|
4076 |
if (np->wolenabled) |
5424 |
if (np->wolenabled) |
4077 |
nv_start_rx(dev); |
5425 |
nv_start_rx(dev); |
4078 |
|
5426 |
|
4079 |
/* special op: write back the misordered MAC address - otherwise |
|
|
4080 |
* the next nv_probe would see a wrong address. |
4081 |
*/ |
4082 |
writel(np->orig_mac[0], base + NvRegMacAddrA); |
4083 |
writel(np->orig_mac[1], base + NvRegMacAddrB); |
4084 |
|
4085 |
/* FIXME: power down nic */ |
5427 |
/* FIXME: power down nic */ |
4086 |
|
5428 |
|
4087 |
return 0; |
5429 |
return 0; |
Lines 4094-4107
Link Here
|
4094 |
unsigned long addr; |
5436 |
unsigned long addr; |
4095 |
u8 __iomem *base; |
5437 |
u8 __iomem *base; |
4096 |
int err, i; |
5438 |
int err, i; |
4097 |
u32 powerstate; |
5439 |
u32 powerstate, phystate_orig = 0, phystate, txreg; |
|
|
5440 |
int phyinitialized = 0; |
4098 |
|
5441 |
|
|
|
5442 |
//NVLAN_DISABLE_ALL_FEATURES ; |
5443 |
/* modify network device class id */ |
5444 |
quirk_nforce_network_class(pci_dev); |
4099 |
dev = alloc_etherdev(sizeof(struct fe_priv)); |
5445 |
dev = alloc_etherdev(sizeof(struct fe_priv)); |
4100 |
err = -ENOMEM; |
5446 |
err = -ENOMEM; |
4101 |
if (!dev) |
5447 |
if (!dev) |
4102 |
goto out; |
5448 |
goto out; |
4103 |
|
5449 |
|
4104 |
np = netdev_priv(dev); |
5450 |
dprintk(KERN_DEBUG "%s:nv_probe: begin\n",dev->name); |
|
|
5451 |
np = get_nvpriv(dev); |
4105 |
np->pci_dev = pci_dev; |
5452 |
np->pci_dev = pci_dev; |
4106 |
spin_lock_init(&np->lock); |
5453 |
spin_lock_init(&np->lock); |
4107 |
SET_MODULE_OWNER(dev); |
5454 |
SET_MODULE_OWNER(dev); |
Lines 4170-4179
Link Here
|
4170 |
dev->features |= NETIF_F_HIGHDMA; |
5517 |
dev->features |= NETIF_F_HIGHDMA; |
4171 |
printk(KERN_INFO "forcedeth: using HIGHDMA\n"); |
5518 |
printk(KERN_INFO "forcedeth: using HIGHDMA\n"); |
4172 |
} |
5519 |
} |
|
|
5520 |
#if NVVER > RHES3 |
4173 |
if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) { |
5521 |
if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) { |
4174 |
printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n", |
5522 |
printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n", |
4175 |
pci_name(pci_dev)); |
5523 |
pci_name(pci_dev)); |
4176 |
} |
5524 |
} |
|
|
5525 |
#endif |
4177 |
} |
5526 |
} |
4178 |
} else if (id->driver_data & DEV_HAS_LARGEDESC) { |
5527 |
} else if (id->driver_data & DEV_HAS_LARGEDESC) { |
4179 |
/* packet format 2: supports jumbo frames */ |
5528 |
/* packet format 2: supports jumbo frames */ |
Lines 4188-4208
Link Here
|
4188 |
np->pkt_limit = NV_PKTLIMIT_1; |
5537 |
np->pkt_limit = NV_PKTLIMIT_1; |
4189 |
if (id->driver_data & DEV_HAS_LARGEDESC) |
5538 |
if (id->driver_data & DEV_HAS_LARGEDESC) |
4190 |
np->pkt_limit = NV_PKTLIMIT_2; |
5539 |
np->pkt_limit = NV_PKTLIMIT_2; |
|
|
5540 |
if (mtu > np->pkt_limit) { |
5541 |
printk(KERN_INFO "forcedeth: MTU value of %d is too large. Setting to maximum value of %d\n", |
5542 |
mtu, np->pkt_limit); |
5543 |
dev->mtu = np->pkt_limit; |
5544 |
} else { |
5545 |
dev->mtu = mtu; |
5546 |
} |
4191 |
|
5547 |
|
4192 |
if (id->driver_data & DEV_HAS_CHECKSUM) { |
5548 |
if (id->driver_data & DEV_HAS_CHECKSUM) { |
4193 |
np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; |
5549 |
if (rx_checksum_offload) { |
4194 |
dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG; |
5550 |
np->rx_csum = 1; |
|
|
5551 |
np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; |
5552 |
} |
5553 |
|
5554 |
if (tx_checksum_offload) |
5555 |
#if NVVER > RHES4 |
5556 |
dev->features |= NETIF_F_HW_CSUM; |
5557 |
#else |
5558 |
dev->features |= NETIF_F_IP_CSUM; |
5559 |
#endif |
5560 |
|
5561 |
if (scatter_gather) |
5562 |
dev->features |= NETIF_F_SG; |
4195 |
#ifdef NETIF_F_TSO |
5563 |
#ifdef NETIF_F_TSO |
4196 |
dev->features |= NETIF_F_TSO; |
5564 |
if (tso_offload) |
|
|
5565 |
dev->features |= NETIF_F_TSO; |
4197 |
#endif |
5566 |
#endif |
4198 |
} |
5567 |
} |
4199 |
|
5568 |
|
4200 |
np->vlanctl_bits = 0; |
5569 |
np->vlanctl_bits = 0; |
4201 |
if (id->driver_data & DEV_HAS_VLAN) { |
5570 |
if (id->driver_data & DEV_HAS_VLAN && tagging_8021pq) { |
4202 |
np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE; |
5571 |
np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE; |
4203 |
dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX; |
5572 |
dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX; |
4204 |
dev->vlan_rx_register = nv_vlan_rx_register; |
5573 |
dev->vlan_rx_register = nv_vlan_rx_register; |
4205 |
dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid; |
5574 |
dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid; |
|
|
5575 |
/* vlan needs rx checksum support, so force it */ |
5576 |
np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; |
4206 |
} |
5577 |
} |
4207 |
|
5578 |
|
4208 |
np->msi_flags = 0; |
5579 |
np->msi_flags = 0; |
Lines 4212-4223
Link Here
|
4212 |
if ((id->driver_data & DEV_HAS_MSI_X) && msix) { |
5583 |
if ((id->driver_data & DEV_HAS_MSI_X) && msix) { |
4213 |
np->msi_flags |= NV_MSI_X_CAPABLE; |
5584 |
np->msi_flags |= NV_MSI_X_CAPABLE; |
4214 |
} |
5585 |
} |
4215 |
|
5586 |
|
4216 |
np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG; |
5587 |
np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE; |
|
|
5588 |
if (rx_flow_control == NV_RX_FLOW_CONTROL_ENABLED) |
5589 |
np->pause_flags |= NV_PAUSEFRAME_RX_REQ; |
4217 |
if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) { |
5590 |
if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) { |
4218 |
np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ; |
5591 |
np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE; |
|
|
5592 |
if (tx_flow_control == NV_TX_FLOW_CONTROL_ENABLED) |
5593 |
np->pause_flags |= NV_PAUSEFRAME_TX_REQ; |
5594 |
} |
5595 |
if (autoneg == AUTONEG_ENABLE) { |
5596 |
np->pause_flags |= NV_PAUSEFRAME_AUTONEG; |
5597 |
} else if (speed_duplex == NV_SPEED_DUPLEX_1000_FULL_DUPLEX) { |
5598 |
printk(KERN_INFO "forcedeth: speed_duplex of 1000 full can not enabled if autoneg is disabled\n"); |
5599 |
goto out_relreg; |
4219 |
} |
5600 |
} |
4220 |
|
|
|
4221 |
|
5601 |
|
4222 |
err = -ENOMEM; |
5602 |
err = -ENOMEM; |
4223 |
np->base = ioremap(addr, np->register_size); |
5603 |
np->base = ioremap(addr, np->register_size); |
Lines 4227-4236
Link Here
|
4227 |
|
5607 |
|
4228 |
dev->irq = pci_dev->irq; |
5608 |
dev->irq = pci_dev->irq; |
4229 |
|
5609 |
|
4230 |
np->rx_ring_size = RX_RING_DEFAULT; |
5610 |
if (np->desc_ver == DESC_VER_1) { |
4231 |
np->tx_ring_size = TX_RING_DEFAULT; |
5611 |
if (rx_ring_size > RING_MAX_DESC_VER_1) { |
4232 |
np->tx_limit_stop = np->tx_ring_size - TX_LIMIT_DIFFERENCE; |
5612 |
printk(KERN_INFO "forcedeth: rx_ring_size of %d is too large. Setting to maximum of %d\n", |
4233 |
np->tx_limit_start = np->tx_ring_size - TX_LIMIT_DIFFERENCE - 1; |
5613 |
rx_ring_size, RING_MAX_DESC_VER_1); |
|
|
5614 |
rx_ring_size = RING_MAX_DESC_VER_1; |
5615 |
} |
5616 |
if (tx_ring_size > RING_MAX_DESC_VER_1) { |
5617 |
printk(KERN_INFO "forcedeth: tx_ring_size of %d is too large. Setting to maximum of %d\n", |
5618 |
tx_ring_size, RING_MAX_DESC_VER_1); |
5619 |
tx_ring_size = RING_MAX_DESC_VER_1; |
5620 |
} |
5621 |
} else { |
5622 |
if (rx_ring_size > RING_MAX_DESC_VER_2_3) { |
5623 |
printk(KERN_INFO "forcedeth: rx_ring_size of %d is too large. Setting to maximum of %d\n", |
5624 |
rx_ring_size, RING_MAX_DESC_VER_2_3); |
5625 |
rx_ring_size = RING_MAX_DESC_VER_2_3; |
5626 |
} |
5627 |
if (tx_ring_size > RING_MAX_DESC_VER_2_3) { |
5628 |
printk(KERN_INFO "forcedeth: tx_ring_size of %d is too large. Setting to maximum of %d\n", |
5629 |
tx_ring_size, RING_MAX_DESC_VER_2_3); |
5630 |
tx_ring_size = RING_MAX_DESC_VER_2_3; |
5631 |
} |
5632 |
} |
5633 |
np->rx_ring_size = rx_ring_size; |
5634 |
np->tx_ring_size = tx_ring_size; |
5635 |
np->tx_limit_stop = tx_ring_size - TX_LIMIT_DIFFERENCE; |
5636 |
np->tx_limit_start = tx_ring_size - TX_LIMIT_DIFFERENCE - 1; |
4234 |
|
5637 |
|
4235 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
5638 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { |
4236 |
np->rx_ring.orig = pci_alloc_consistent(pci_dev, |
5639 |
np->rx_ring.orig = pci_alloc_consistent(pci_dev, |
Lines 4247-4275
Link Here
|
4247 |
goto out_unmap; |
5650 |
goto out_unmap; |
4248 |
np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; |
5651 |
np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; |
4249 |
} |
5652 |
} |
4250 |
np->rx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->rx_ring_size, GFP_KERNEL); |
5653 |
np->rx_skb = kmalloc(sizeof(struct nv_skb_map) * np->rx_ring_size, GFP_KERNEL); |
4251 |
np->rx_dma = kmalloc(sizeof(dma_addr_t) * np->rx_ring_size, GFP_KERNEL); |
5654 |
np->tx_skb = kmalloc(sizeof(struct nv_skb_map) * np->tx_ring_size, GFP_KERNEL); |
4252 |
np->tx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->tx_ring_size, GFP_KERNEL); |
5655 |
if (!np->rx_skb || !np->tx_skb) |
4253 |
np->tx_dma = kmalloc(sizeof(dma_addr_t) * np->tx_ring_size, GFP_KERNEL); |
|
|
4254 |
np->tx_dma_len = kmalloc(sizeof(unsigned int) * np->tx_ring_size, GFP_KERNEL); |
4255 |
if (!np->rx_skbuff || !np->rx_dma || !np->tx_skbuff || !np->tx_dma || !np->tx_dma_len) |
4256 |
goto out_freering; |
5656 |
goto out_freering; |
4257 |
memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size); |
5657 |
memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size); |
4258 |
memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size); |
5658 |
memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size); |
4259 |
memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size); |
|
|
4260 |
memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size); |
4261 |
memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size); |
4262 |
|
5659 |
|
4263 |
dev->open = nv_open; |
5660 |
dev->open = nv_open; |
4264 |
dev->stop = nv_close; |
5661 |
dev->stop = nv_close; |
4265 |
dev->hard_start_xmit = nv_start_xmit; |
5662 |
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) |
|
|
5663 |
dev->hard_start_xmit = nv_start_xmit; |
5664 |
else |
5665 |
dev->hard_start_xmit = nv_start_xmit_optimized; |
4266 |
dev->get_stats = nv_get_stats; |
5666 |
dev->get_stats = nv_get_stats; |
4267 |
dev->change_mtu = nv_change_mtu; |
5667 |
dev->change_mtu = nv_change_mtu; |
4268 |
dev->set_mac_address = nv_set_mac_address; |
5668 |
dev->set_mac_address = nv_set_mac_address; |
4269 |
dev->set_multicast_list = nv_set_multicast; |
5669 |
dev->set_multicast_list = nv_set_multicast; |
|
|
5670 |
|
5671 |
#if NVVER < SLES9 |
5672 |
dev->do_ioctl = nv_ioctl; |
5673 |
#endif |
5674 |
|
5675 |
#if NVVER > RHES3 |
4270 |
#ifdef CONFIG_NET_POLL_CONTROLLER |
5676 |
#ifdef CONFIG_NET_POLL_CONTROLLER |
4271 |
dev->poll_controller = nv_poll_controller; |
5677 |
dev->poll_controller = nv_poll_controller; |
4272 |
#endif |
5678 |
#endif |
|
|
5679 |
#else |
5680 |
dev->poll_controller = nv_poll_controller; |
5681 |
#endif |
5682 |
|
4273 |
SET_ETHTOOL_OPS(dev, &ops); |
5683 |
SET_ETHTOOL_OPS(dev, &ops); |
4274 |
dev->tx_timeout = nv_tx_timeout; |
5684 |
dev->tx_timeout = nv_tx_timeout; |
4275 |
dev->watchdog_timeo = NV_WATCHDOG_TIMEO; |
5685 |
dev->watchdog_timeo = NV_WATCHDOG_TIMEO; |
Lines 4281-4295
Link Here
|
4281 |
np->orig_mac[0] = readl(base + NvRegMacAddrA); |
5691 |
np->orig_mac[0] = readl(base + NvRegMacAddrA); |
4282 |
np->orig_mac[1] = readl(base + NvRegMacAddrB); |
5692 |
np->orig_mac[1] = readl(base + NvRegMacAddrB); |
4283 |
|
5693 |
|
|
|
5694 |
/* check the workaround bit for correct mac address order */ |
5695 |
txreg = readl(base + NvRegTransmitPoll); |
5696 |
if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) { |
5697 |
/* mac address is already in correct order */ |
5698 |
dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff; |
5699 |
dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff; |
5700 |
dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff; |
5701 |
dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff; |
5702 |
dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff; |
5703 |
dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff; |
5704 |
} else { |
4284 |
dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff; |
5705 |
dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff; |
4285 |
dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff; |
5706 |
dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff; |
4286 |
dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff; |
5707 |
dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff; |
4287 |
dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff; |
5708 |
dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff; |
4288 |
dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff; |
5709 |
dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff; |
4289 |
dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff; |
5710 |
dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff; |
|
|
5711 |
/* set permanent address to be correct aswell */ |
5712 |
np->orig_mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) + |
5713 |
(dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24); |
5714 |
np->orig_mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8); |
5715 |
writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); |
5716 |
} |
5717 |
#if NVVER > SUSE10 |
4290 |
memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
5718 |
memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
4291 |
|
5719 |
|
4292 |
if (!is_valid_ether_addr(dev->perm_addr)) { |
5720 |
if (!is_valid_ether_addr(dev->perm_addr)) { |
|
|
5721 |
#else |
5722 |
if (!is_valid_ether_addr(dev->dev_addr)) { |
5723 |
#endif |
4293 |
/* |
5724 |
/* |
4294 |
* Bad mac address. At least one bios sets the mac address |
5725 |
* Bad mac address. At least one bios sets the mac address |
4295 |
* to 01:23:45:67:89:ab |
5726 |
* to 01:23:45:67:89:ab |
Lines 4308-4317
Link Here
|
4308 |
dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev), |
5739 |
dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev), |
4309 |
dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], |
5740 |
dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], |
4310 |
dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); |
5741 |
dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); |
|
|
5742 |
/* set mac address */ |
5743 |
nv_copy_mac_to_hw(dev); |
4311 |
|
5744 |
|
4312 |
/* disable WOL */ |
5745 |
/* disable WOL */ |
4313 |
writel(0, base + NvRegWakeUpFlags); |
5746 |
writel(0, base + NvRegWakeUpFlags); |
4314 |
np->wolenabled = 0; |
5747 |
np->wolenabled = wol; |
4315 |
|
5748 |
|
4316 |
if (id->driver_data & DEV_HAS_POWER_CNTRL) { |
5749 |
if (id->driver_data & DEV_HAS_POWER_CNTRL) { |
4317 |
u8 revision_id; |
5750 |
u8 revision_id; |
Lines 4353-4358
Link Here
|
4353 |
np->need_linktimer = 0; |
5786 |
np->need_linktimer = 0; |
4354 |
} |
5787 |
} |
4355 |
|
5788 |
|
|
|
5789 |
/* clear phy state and temporarily halt phy interrupts */ |
5790 |
writel(0, base + NvRegMIIMask); |
5791 |
phystate = readl(base + NvRegAdapterControl); |
5792 |
if (phystate & NVREG_ADAPTCTL_RUNNING) { |
5793 |
phystate_orig = 1; |
5794 |
phystate &= ~NVREG_ADAPTCTL_RUNNING; |
5795 |
writel(phystate, base + NvRegAdapterControl); |
5796 |
} |
5797 |
writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus); |
5798 |
|
5799 |
if (id->driver_data & DEV_HAS_MGMT_UNIT) { |
5800 |
writel(NV_UNKNOWN_VAL, base + NvRegPatternCRC); |
5801 |
pci_push(base); |
5802 |
nv_msleep(500); |
5803 |
/* management unit running on the mac? */ |
5804 |
np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST; |
5805 |
if (np->mac_in_use) { |
5806 |
u32 mgmt_sync; |
5807 |
dprintk(KERN_DEBUG "%s: probe: mac in use\n",dev->name); |
5808 |
/* management unit setup the phy already? */ |
5809 |
mgmt_sync = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK; |
5810 |
if (mgmt_sync == NVREG_XMITCTL_SYNC_NOT_READY) { |
5811 |
dprintk(KERN_DEBUG"%s : probe: sync not ready\n",dev->name); |
5812 |
if (!nv_mgmt_acquire_sema(dev)) { |
5813 |
dprintk(KERN_DEBUG"%s: probe: could not acquire sema\n",dev->name); |
5814 |
for (i = 0; i < 5000; i++) { |
5815 |
nv_msleep(1); |
5816 |
mgmt_sync = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK; |
5817 |
if (mgmt_sync == NVREG_XMITCTL_SYNC_NOT_READY) |
5818 |
continue; |
5819 |
if (mgmt_sync == NVREG_XMITCTL_SYNC_PHY_INIT) { |
5820 |
dprintk(KERN_DEBUG"%s: probe: phy inited by SMU 1\n",dev->name); |
5821 |
phyinitialized = 1; |
5822 |
} |
5823 |
break; |
5824 |
dprintk(KERN_DEBUG"%s: probe: breaking out of loop\n",dev->name); |
5825 |
} |
5826 |
} else { |
5827 |
/* we need to init the phy */ |
5828 |
dprintk(KERN_DEBUG"%s: probe: we need to init phy 1\n",dev->name); |
5829 |
} |
5830 |
} else if (mgmt_sync == NVREG_XMITCTL_SYNC_PHY_INIT) { |
5831 |
dprintk(KERN_DEBUG"%s: probe: phy inited by SMU 2\n",dev->name); |
5832 |
/* phy is inited by SMU */ |
5833 |
phyinitialized = 1; |
5834 |
} else { |
5835 |
/* we need to init the phy */ |
5836 |
dprintk(KERN_DEBUG"%s: probe: we need to init phy 2\n",dev->name); |
5837 |
} |
5838 |
} else |
5839 |
dprintk(KERN_DEBUG"%s: probe: mac not in use\n",dev->name); |
5840 |
} |
5841 |
|
4356 |
/* find a suitable phy */ |
5842 |
/* find a suitable phy */ |
4357 |
for (i = 1; i <= 32; i++) { |
5843 |
for (i = 1; i <= 32; i++) { |
4358 |
int id1, id2; |
5844 |
int id1, id2; |
Lines 4369-4374
Link Here
|
4369 |
if (id2 < 0 || id2 == 0xffff) |
5855 |
if (id2 < 0 || id2 == 0xffff) |
4370 |
continue; |
5856 |
continue; |
4371 |
|
5857 |
|
|
|
5858 |
np->phy_model = id2 & PHYID2_MODEL_MASK; |
4372 |
id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT; |
5859 |
id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT; |
4373 |
id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT; |
5860 |
id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT; |
4374 |
dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n", |
5861 |
dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n", |
Lines 4382-4395
Link Here
|
4382 |
pci_name(pci_dev)); |
5869 |
pci_name(pci_dev)); |
4383 |
goto out_error; |
5870 |
goto out_error; |
4384 |
} |
5871 |
} |
4385 |
|
5872 |
|
|
|
5873 |
if (!phyinitialized) { |
4386 |
/* reset it */ |
5874 |
/* reset it */ |
4387 |
phy_init(dev); |
5875 |
phy_init(dev); |
|
|
5876 |
} else { |
5877 |
/* see if gigabit phy */ |
5878 |
u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); |
5879 |
if (mii_status & PHY_GIGABIT) { |
5880 |
np->gigabit = PHY_GIGABIT; |
5881 |
} |
5882 |
} |
5883 |
if (id->driver_data & DEV_HAS_MGMT_UNIT) { |
5884 |
nv_mgmt_driver_loaded(dev, 1); |
5885 |
} |
4388 |
|
5886 |
|
4389 |
/* set default link speed settings */ |
5887 |
/* set default link speed settings */ |
4390 |
np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
5888 |
np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
4391 |
np->duplex = 0; |
5889 |
np->duplex = 0; |
4392 |
np->autoneg = 1; |
5890 |
np->autoneg = autoneg; |
4393 |
|
5891 |
|
4394 |
err = register_netdev(dev); |
5892 |
err = register_netdev(dev); |
4395 |
if (err) { |
5893 |
if (err) { |
Lines 4403-4408
Link Here
|
4403 |
return 0; |
5901 |
return 0; |
4404 |
|
5902 |
|
4405 |
out_error: |
5903 |
out_error: |
|
|
5904 |
if (phystate_orig) |
5905 |
writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl); |
5906 |
if (np->mac_in_use) |
5907 |
nv_mgmt_driver_loaded(dev, 0); |
4406 |
pci_set_drvdata(pci_dev, NULL); |
5908 |
pci_set_drvdata(pci_dev, NULL); |
4407 |
out_freering: |
5909 |
out_freering: |
4408 |
free_rings(dev); |
5910 |
free_rings(dev); |
Lines 4421-4428
Link Here
|
4421 |
static void __devexit nv_remove(struct pci_dev *pci_dev) |
5923 |
static void __devexit nv_remove(struct pci_dev *pci_dev) |
4422 |
{ |
5924 |
{ |
4423 |
struct net_device *dev = pci_get_drvdata(pci_dev); |
5925 |
struct net_device *dev = pci_get_drvdata(pci_dev); |
|
|
5926 |
struct fe_priv *np = get_nvpriv(dev); |
5927 |
u8 __iomem *base = get_hwbase(dev); |
4424 |
|
5928 |
|
4425 |
unregister_netdev(dev); |
5929 |
unregister_netdev(dev); |
|
|
5930 |
/* special op: write back the misordered MAC address - otherwise |
5931 |
* the next nv_probe would see a wrong address. |
5932 |
*/ |
5933 |
writel(np->orig_mac[0], base + NvRegMacAddrA); |
5934 |
writel(np->orig_mac[1], base + NvRegMacAddrB); |
5935 |
if (np->mac_in_use) |
5936 |
nv_mgmt_driver_loaded(dev, 0); |
4426 |
|
5937 |
|
4427 |
/* free all structures */ |
5938 |
/* free all structures */ |
4428 |
free_rings(dev); |
5939 |
free_rings(dev); |
Lines 4488-4530
Link Here
|
4488 |
}, |
5999 |
}, |
4489 |
{ /* MCP55 Ethernet Controller */ |
6000 |
{ /* MCP55 Ethernet Controller */ |
4490 |
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14), |
6001 |
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14), |
4491 |
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, |
6002 |
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, |
4492 |
}, |
6003 |
}, |
4493 |
{ /* MCP55 Ethernet Controller */ |
6004 |
{ /* MCP55 Ethernet Controller */ |
4494 |
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15), |
6005 |
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15), |
4495 |
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, |
6006 |
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, |
4496 |
}, |
6007 |
}, |
4497 |
{ /* MCP61 Ethernet Controller */ |
6008 |
{ /* MCP61 Ethernet Controller */ |
4498 |
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16), |
6009 |
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16), |
4499 |
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, |
6010 |
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, |
4500 |
}, |
6011 |
}, |
4501 |
{ /* MCP61 Ethernet Controller */ |
6012 |
{ /* MCP61 Ethernet Controller */ |
4502 |
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17), |
6013 |
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17), |
4503 |
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, |
6014 |
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, |
4504 |
}, |
6015 |
}, |
4505 |
{ /* MCP61 Ethernet Controller */ |
6016 |
{ /* MCP61 Ethernet Controller */ |
4506 |
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18), |
6017 |
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18), |
4507 |
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, |
6018 |
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, |
4508 |
}, |
6019 |
}, |
4509 |
{ /* MCP61 Ethernet Controller */ |
6020 |
{ /* MCP61 Ethernet Controller */ |
4510 |
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19), |
6021 |
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19), |
4511 |
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, |
6022 |
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, |
4512 |
}, |
6023 |
}, |
4513 |
{ /* MCP65 Ethernet Controller */ |
6024 |
{ /* MCP65 Ethernet Controller */ |
4514 |
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20), |
6025 |
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20), |
4515 |
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, |
6026 |
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, |
4516 |
}, |
6027 |
}, |
4517 |
{ /* MCP65 Ethernet Controller */ |
6028 |
{ /* MCP65 Ethernet Controller */ |
4518 |
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21), |
6029 |
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21), |
4519 |
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, |
6030 |
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, |
4520 |
}, |
6031 |
}, |
4521 |
{ /* MCP65 Ethernet Controller */ |
6032 |
{ /* MCP65 Ethernet Controller */ |
4522 |
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22), |
6033 |
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22), |
4523 |
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, |
6034 |
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, |
4524 |
}, |
6035 |
}, |
4525 |
{ /* MCP65 Ethernet Controller */ |
6036 |
{ /* MCP65 Ethernet Controller */ |
4526 |
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23), |
6037 |
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23), |
4527 |
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED, |
6038 |
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT, |
4528 |
}, |
6039 |
}, |
4529 |
{0,}, |
6040 |
{0,}, |
4530 |
}; |
6041 |
}; |
Lines 4540-4545
Link Here
|
4540 |
static int __init init_nic(void) |
6051 |
static int __init init_nic(void) |
4541 |
{ |
6052 |
{ |
4542 |
printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION); |
6053 |
printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION); |
|
|
6054 |
dprintk(KERN_DEBUG "DEBUG VERSION\n"); |
4543 |
return pci_module_init(&driver); |
6055 |
return pci_module_init(&driver); |
4544 |
} |
6056 |
} |
4545 |
|
6057 |
|
Lines 4548-4553
Link Here
|
4548 |
pci_unregister_driver(&driver); |
6060 |
pci_unregister_driver(&driver); |
4549 |
} |
6061 |
} |
4550 |
|
6062 |
|
|
|
6063 |
#if NVVER > SLES9 |
4551 |
module_param(max_interrupt_work, int, 0); |
6064 |
module_param(max_interrupt_work, int, 0); |
4552 |
MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt"); |
6065 |
MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt"); |
4553 |
module_param(optimization_mode, int, 0); |
6066 |
module_param(optimization_mode, int, 0); |
Lines 4558-4566
Link Here
|
4558 |
MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0."); |
6071 |
MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0."); |
4559 |
module_param(msix, int, 0); |
6072 |
module_param(msix, int, 0); |
4560 |
MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0."); |
6073 |
MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0."); |
|
|
6074 |
|
6075 |
module_param(speed_duplex, int, 0); |
6076 |
MODULE_PARM_DESC(speed_duplex, "PHY speed and duplex settings. Auto = 0, 10mbps half = 1, 10mbps full = 2, 100mbps half = 3, 100mbps full = 4, 1000mbps full = 5."); |
6077 |
module_param(autoneg, int, 0); |
6078 |
MODULE_PARM_DESC(autoneg, "PHY autonegotiate is enabled by setting to 1 and disabled by setting to 0."); |
6079 |
module_param(scatter_gather, int, 0); |
6080 |
MODULE_PARM_DESC(scatter_gather, "Scatter gather is enabled by setting to 1 and disabled by setting to 0."); |
6081 |
module_param(tso_offload, int, 0); |
6082 |
MODULE_PARM_DESC(tso_offload, "TCP Segmentation offload is enabled by setting to 1 and disabled by setting to 0."); |
6083 |
module_param(mtu, int, 0); |
6084 |
MODULE_PARM_DESC(mtu, "MTU value. Maximum value of 1500 or 9100 depending on hardware."); |
6085 |
module_param(tx_checksum_offload, int, 0); |
6086 |
MODULE_PARM_DESC(tx_checksum_offload, "Tx checksum offload is enabled by setting to 1 and disabled by setting to 0."); |
6087 |
module_param(rx_checksum_offload, int, 0); |
6088 |
MODULE_PARM_DESC(rx_checksum_offload, "Rx checksum offload is enabled by setting to 1 and disabled by setting to 0."); |
6089 |
module_param(tx_ring_size, int, 0); |
6090 |
MODULE_PARM_DESC(tx_ring_size, "Tx ring size. Maximum value of 1024 or 16384 depending on hardware."); |
6091 |
module_param(rx_ring_size, int, 0); |
6092 |
MODULE_PARM_DESC(rx_ring_size, "Rx ring size. Maximum value of 1024 or 16384 depending on hardware."); |
6093 |
module_param(tx_flow_control, int, 0); |
6094 |
MODULE_PARM_DESC(tx_flow_control, "Tx flow control is enabled by setting to 1 and disabled by setting to 0."); |
6095 |
module_param(rx_flow_control, int, 0); |
6096 |
MODULE_PARM_DESC(rx_flow_control, "Rx flow control is enabled by setting to 1 and disabled by setting to 0."); |
4561 |
module_param(dma_64bit, int, 0); |
6097 |
module_param(dma_64bit, int, 0); |
4562 |
MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0."); |
6098 |
MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0."); |
4563 |
|
6099 |
module_param(wol, int, 0); |
|
|
6100 |
MODULE_PARM_DESC(wol, "Wake-On-Lan is enabled by setting to 1 and disabled by setting to 0."); |
6101 |
module_param(tagging_8021pq, int, 0); |
6102 |
MODULE_PARM_DESC(tagging_8021pq, "802.1pq tagging is enabled by setting to 1 and disabled by setting to 0."); |
6103 |
#else |
6104 |
MODULE_PARM(max_interrupt_work, "i"); |
6105 |
MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt"); |
6106 |
MODULE_PARM(optimization_mode, "i"); |
6107 |
MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer."); |
6108 |
MODULE_PARM(poll_interval, "i"); |
6109 |
MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535."); |
6110 |
#ifdef CONFIG_PCI_MSI |
6111 |
MODULE_PARM(msi, "i"); |
6112 |
MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0."); |
6113 |
MODULE_PARM(msix, "i"); |
6114 |
MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0."); |
6115 |
#endif |
6116 |
MODULE_PARM(speed_duplex, "i"); |
6117 |
MODULE_PARM_DESC(speed_duplex, "PHY speed and duplex settings. Auto = 0, 10mbps half = 1, 10mbps full = 2, 100mbps half = 3, 100mbps full = 4, 1000mbps full = 5."); |
6118 |
MODULE_PARM(autoneg, "i"); |
6119 |
MODULE_PARM_DESC(autoneg, "PHY autonegotiate is enabled by setting to 1 and disabled by setting to 0."); |
6120 |
MODULE_PARM(scatter_gather, "i"); |
6121 |
MODULE_PARM_DESC(scatter_gather, "Scatter gather is enabled by setting to 1 and disabled by setting to 0."); |
6122 |
MODULE_PARM(tso_offload, "i"); |
6123 |
MODULE_PARM_DESC(tso_offload, "TCP Segmentation offload is enabled by setting to 1 and disabled by setting to 0."); |
6124 |
MODULE_PARM(mtu, "i"); |
6125 |
MODULE_PARM_DESC(mtu, "MTU value. Maximum value of 1500 or 9100 depending on hardware."); |
6126 |
MODULE_PARM(tx_checksum_offload, "i"); |
6127 |
MODULE_PARM_DESC(tx_checksum_offload, "Tx checksum offload is enabled by setting to 1 and disabled by setting to 0."); |
6128 |
MODULE_PARM(rx_checksum_offload, "i"); |
6129 |
MODULE_PARM_DESC(rx_checksum_offload, "Rx checksum offload is enabled by setting to 1 and disabled by setting to 0."); |
6130 |
MODULE_PARM(tx_ring_size, "i"); |
6131 |
MODULE_PARM_DESC(tx_ring_size, "Tx ring size. Maximum value of 1024 or 16384 depending on hardware."); |
6132 |
MODULE_PARM(rx_ring_size, "i"); |
6133 |
MODULE_PARM_DESC(rx_ring_size, "Rx ring size. Maximum value of 1024 or 16384 depending on hardware."); |
6134 |
MODULE_PARM(tx_flow_control, "i"); |
6135 |
MODULE_PARM_DESC(tx_flow_control, "Tx flow control is enabled by setting to 1 and disabled by setting to 0."); |
6136 |
MODULE_PARM(rx_flow_control, "i"); |
6137 |
MODULE_PARM_DESC(rx_flow_control, "Rx flow control is enabled by setting to 1 and disabled by setting to 0."); |
6138 |
MODULE_PARM(dma_64bit, "i"); |
6139 |
MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0."); |
6140 |
MODULE_PARM(wol, "i"); |
6141 |
MODULE_PARM_DESC(wol, "Wake-On-Lan is enabled by setting to 1 and disabled by setting to 0."); |
6142 |
MODULE_PARM(tagging_8021pq, "i"); |
6143 |
MODULE_PARM_DESC(tagging_8021pq, "802.1pq tagging is enabled by setting to 1 and disabled by setting to 0."); |
6144 |
#endif |
4564 |
MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>"); |
6145 |
MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>"); |
4565 |
MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver"); |
6146 |
MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver"); |
4566 |
MODULE_LICENSE("GPL"); |
6147 |
MODULE_LICENSE("GPL"); |